Redistribution Layer Protrusions for Signal Timing Control
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Solution Overview
Problem
The meander line layout routing method in chip design, while enhancing signal transmission quality, is limited by chip size and becomes complicated, making it challenging to further improve high-speed signal transmission quality.
Innovation Solution
A chip structure with a redistribution layer featuring conductive traces that include a body and protrusions, allowing for adjustment of equivalent parasitic capacitance and inductance to match delay times of conductive traces, thereby optimizing signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If meander line layout routing method is used, then timing control and signal transmission quality are improved, but chip area utilization becomes inefficient and design complexity increases
Solution Approach 1:
The patent applies local quality by adding protrusions only to specific conductive traces that require timing adjustment, rather than using complex meander patterns throughout the entire redistribution layer. Each protrusion is locally positioned to provide the necessary delay adjustment for particular signal paths, simplifying the overall design while maintaining timing control.
Solution Approach 2:
The patent changes the physical parameter of the conductive traces by adding protrusions with specific dimensions (width, length, position) to adjust the electrical characteristics (parasitic capacitance and inductance) of selected traces. This allows timing control through parameter modification rather than through complex routing patterns.
2Reliability
If meander line layout routing method is used, then signal transmission quality is enhanced, but chip size becomes a limiting factor
Solution Approach 1:
Instead of using area-intensive meander patterns across the entire chip, the patent applies local protrusions only where timing adjustment is needed. This localized approach maintains signal transmission quality for critical paths while preserving chip area for other functional elements.
Solution Approach 2:
The patent transitions from two-dimensional meander line routing to a three-dimensional conductive trace structure by adding protrusions that extend in the vertical dimension (through the dielectric layer). This dimensional change allows timing adjustment without increasing the planar chip area.
Data Source
AI summary
A chip structure including a chip and a redistribution layer is provided. The chip includes a plurality of pads. The redistribution layer includes a dielectric layer and a plurality of conductive traces. The dielectric layer is disposed on the chip and has a plurality of contact windows located above the pads. The conductive traces are located on the dielectric layer and are electrically coupled to the pads through the contact windows. At least one of the conductive traces includes a body and at least one protrusion coupled to the body, and the at least one protrusion is coupled to an area of the body other than where the contact windows are coupled to on the body.