Redistribution Layer Routing for 2.5D IC Packages
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Solution Overview
Problem
Traditional 2.5D IC packaging technologies face challenges in efficiently routing inter-chip nets with variable wire widths and spacings, leading to increased routing complexity and signal coupling effects that degrade circuit performance.
Innovation Solution
A unified redistribution layer (RDL) routing framework using the modulus-based matrix splitting iteration method (MMSIM) and minimum weighted maximum cardinality bipartite matching (MWMCBM) to assign pre-assignment nets to tracks, minimizing total vertical distance and ensuring design rules are met, while allowing for both grid-based and gridless designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If variable wire widths and spacings are adopted to improve circuit performance, then routing flexibility and circuit performance are improved, but routing complexity increases dramatically
Solution Approach 1:
The routing problem is divided into two distinct phases: global routing that determines wire paths and track assignments, and detailed routing that handles local connections within tracks. This segmentation allows variable widths and spacings to be managed systematically in the global routing phase while simplifying the detailed routing phase, thereby reducing overall routing complexity while maintaining performance benefits.
Solution Approach 2:
The invention systematically varies wire widths and spacings as design parameters to optimize circuit performance. By treating these as controllable parameters rather than fixed values, the routing algorithm can adapt wire dimensions to meet timing and power constraints while managing complexity through structured parameter optimization frameworks.
2Device complexity
If traditional uniform wire widths and spacings are used, then routing complexity is reduced, but circuit performance optimization is limited
Solution Approach 1:
Different regions of the routing structure are assigned different wire widths and spacings based on local performance requirements. Critical signal paths receive optimized dimensions while less critical paths use standard dimensions, achieving performance optimization without uniformly increasing complexity across the entire design.
3Area of stationary object
If wires are routed closely together to reduce area, then area utilization is improved, but signal coupling effects increase and degrade signal integrity
Solution Approach 1:
Power or ground nets are introduced as intermediary elements between signal-carrying wires. These intermediary nets act as shields that reduce electromagnetic coupling between adjacent signal wires, allowing closer wire spacing for better area utilization while maintaining signal integrity through the protective effect of the power/ground shielding layers.
4Object-affected harmful factors
If power/ground nets are interleaved with signal wires to reduce coupling, then signal integrity is improved, but routing complexity increases
Solution Approach 1:
The routing of power/ground nets and signal wires is merged into a unified routing process rather than treating them as separate tasks. The algorithm simultaneously determines the placement and routing of both net types, optimizing their interleaved arrangement to reduce coupling while managing complexity through integrated optimization rather than sequential processing.
Data Source
AI summary
A method of redistribution layer routing for 2.5D integrated circuit packages is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a MMSIM (modulus-based matrix splitting iteration method) based routing to assign pre-assignment nets to tracks such that total vertical distance from each bump pair to the assigned track is minimized; and performing a MWMCBM (minimum weighted maximum cardinality bipartite matching) based routing for bumps connected to the assigned tracks according to matching result to complete redistribution layer routing for integrated circuit packages.