Redistribution Layer Signal Routing for Semiconductor Chip Size Reduction
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Solution Overview
Problem
Traditional semiconductor devices face challenges in efficiently routing signals and power within the chip, leading to increased size and complexity due to the need for extensive metal layers and bond pads, which are costly and space-consuming.
Innovation Solution
Incorporating a redistribution layer with signal routing lines and vias that reroute signals from the center to the edge of the chip, allowing power and other signals to be delivered above the passivation layers, reducing the need for additional metal layers and bond pads, and using conventional fabrication techniques for the redistribution layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If signals are routed through traditional metal layers and bond pads, then electrical connection is achieved, but chip size increases and manufacturing cost increases
Solution Approach 1:
The patent introduces a redistribution layer positioned above the passivation layer, creating a new dimensional plane for signal routing. This allows signals to be routed in a third dimension (above the traditional metal layers), reducing the need for extensive lateral routing on the chip surface and minimizing chip size while maintaining signal routing capability.
Solution Approach 2:
The redistribution layer acts as an intermediary between the bond pads and the final signal destinations. By introducing this intermediate routing layer with vias connecting to underlying metal layers, the patent enables more efficient signal paths that reduce overall chip area requirements while maintaining reliable electrical connections.
2Reliability
If extensive metal layers and bond pads are used for signal routing, then signal delivery is achieved, but manufacturing cost increases
Solution Approach 1:
The patent segments the signal routing function across multiple layers: traditional metal layers for internal chip interconnection and a separate redistribution layer for external signal routing. This segmentation allows each layer to be optimized independently, reducing the need for extensive metal layers while maintaining signal delivery capability, thereby lowering manufacturing costs.
Solution Approach 2:
The redistribution layer serves multiple functions: it redistributes signals from bond pads to internal destinations, provides additional routing capacity, and enables customization for different packaging applications. This multi-functionality reduces the need for separate dedicated metal layers, lowering manufacturing complexity and cost while maintaining robust signal delivery.
3Adaptability or versatility
If redistribution layer is added after chip fabrication, then design flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates the redistribution layer as part of the final fabrication steps, preparing the routing infrastructure in advance before chip assembly. By establishing the redistribution network during manufacturing rather than requiring post-fabrication modification, the patent achieves design flexibility while actually simplifying the overall manufacturing process.
Solution Approach 2:
The redistribution layer uses standard photolithography and thin-film deposition techniques that replicate proven manufacturing processes. By copying established fabrication methods rather than introducing novel complex processes, the patent achieves design adaptability while maintaining manufacturing simplicity and consistency with existing production capabilities.
Data Source
AI summary
A semiconductor wafer has a dielectric layer, a metal last layer, a passivation layer, and a redistribution layer. The metal last layer is formed over the dielectric layer, and the metal last layer has first and second locations that are spaced apart from each other. The passivation layer is formed over the metal last layer. The redistribution layer is formed over the passivation layer. The redistribution layer has a signal routing wire coupled to the first location of the metal last layer and to the second location of the metal last layer.