Redistribution Layer Structure With Segmented Vias for Flatness
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Solution Overview
Problem
The existing redistribution layer (RDL) process in semiconductor devices faces challenges with via hole size, leading to topology issues such as bending and sagging, which result in electrical short circuits and reduced reliability, especially as chip sizes decrease and patterns become finer.
Innovation Solution
The proposed redistribution layer structure includes a first insulating layer with multiple small openings or a ring-shaped opening, accompanied by an unetched portion to improve flatness, and a wiring member layer that fills these openings, ensuring excellent electrical connectivity while preventing bending and sagging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the via hole is large to improve electrical connectivity, then electrical connectivity is improved, but topology problems such as bending and sagging occur in the redistribution layer
Solution Approach 1:
The patent divides a single large via hole into multiple smaller via holes arranged in an array within the same target region. This segmentation maintains electrical connectivity by providing multiple conduction paths while preventing the topology problems (bending and sagging) that occur with large via holes. The multiple small via holes distribute the electrical load and structural stress, resolving the contradiction between connectivity and shape stability.
2Shape
If the size of the via hole is reduced to tens of micrometers or less to prevent topology problems, then topology is improved, but electrical connectivity may be compromised
Solution Approach 1:
The patent combines multiple small via holes into a unified array structure that functions as a single electrical connection system. By merging the functionality of multiple small via holes while maintaining their individual small sizes, the invention achieves both improved topology (no bending or sagging) and maintained electrical connectivity (multiple parallel conduction paths).
Data Source
AI summary
Disclosed are a redistribution layer structure, a method of forming a redistribution layer structure, a semiconductor package device including a redistribution layer structure, and a method of manufacturing a semiconductor package device including a redistribution layer structure. The semiconductor package device may include a redistribution layer structure, wherein the redistribution layer structure may include a first insulating layer having one or more openings open to a target region and an unetched portion configured to improve the flatness of the redistribution layer structure in the remaining region excluding the one or more openings in the space corresponding to the target region and a first wiring member layer disposed on the first insulating layer so as to at least partially fill the one or more openings.