Redistribution Layer Selection Unit for 3D Stacked Semiconductor Devices
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Solution Overview
Problem
In 3D stacked semiconductor devices, the redistribution layer (RDL) used for IO extension often collides, overlaps, or intersects with TSV lines, complicating packaging and increasing production costs due to the need for separate masks and complex wiring.
Innovation Solution
A semiconductor device with a selection unit that controls the connection between redistribution layers and I/O units using logic-level selection signals, allowing for independent management of pad connections to prevent collisions or intersections with TSV lines, and enabling the use of a single mask for patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a redistribution layer is used for IO extension in 3D stacked semiconductor devices, then the number of I/O ports is increased, but the RDL collides, overlaps, or intersects with TSV lines complicating packaging
Solution Approach 1:
The patent implements a selection unit that dynamically switches the connection between the first RDL and the first I/O unit, and between the second RDL and the first I/O unit, based on logic-level selection signals. This dynamic switching capability allows the system to adaptively manage signal routing, enabling increased I/O ports without permanent physical collisions or intersections with TSV lines, thereby resolving the contradiction between IO extension and packaging complexity
Solution Approach 2:
The patent divides the redistribution layer into multiple segments (first RDL and second RDL) that can be independently controlled through the selection unit. By segmenting the RDL and enabling selective connection to I/O units, the design avoids the need for a single complex RDL that would collide with TSV lines, thus increasing I/O capacity while simplifying packaging
2Ease of operation
If separate chip selection pins are used for each chip, then chip selection is enabled, but the chip area is reduced and the number of selectable chips is limited
Solution Approach 1:
The selection unit serves multiple functions: it selectively connects different RDLs to the I/O unit, acts as a chip selection mechanism, and enables multiple chips to be selected without dedicated selection pins for each chip. This multi-functional approach maintains chip selection capability while preserving chip area and increasing the number of selectable chips
3Reliability
If wire coupling is used to connect voltage input terminal to chip selection pin, then voltage delivery is achieved, but lines become complicated
Solution Approach 1:
The patent combines the voltage delivery function and chip selection function into a single integrated structure. The selection unit receives both voltage signals and selection signals, eliminating the need for separate wire couplings between voltage input terminals and chip selection pins. This merging reduces wiring complexity while maintaining reliable voltage delivery for chip selection
4Ease of operation
If oblique stacking of chips is used, then chip selection is possible, but packaging becomes complicated and difficult
Solution Approach 1:
The patent replaces static oblique stacking with a dynamic electrical switching mechanism. The selection unit dynamically switches connections based on selection signals, eliminating the need for physical oblique stacking. This maintains chip selection capability while dramatically simplifying packaging and manufacturing processes
Data Source
AI summary
A semiconductor device may include a first redistribution layer configured to allow for input and output of a first signal through the first redistribution layer. The semiconductor device may include a second redistribution layer configured to allow for input and output of a second signal through the second redistribution layer. The semiconductor device may include a first input/output (I/O) unit configured to input and output the first signal or the second signal through the first I/O unit. The semiconductor device may include a first selection unit configured to selectively couple a connection among the first redistribution layer, the second redistribution layer, and the first I/O unit in response to a logic level of a first selection signal. The semiconductor device may include a first selection signal generation unit configured to generate the first selection signal.