Redistribution Layer Design for Compact Semiconductor Packages
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Solution Overview
Problem
Conventional semiconductor package designs face limitations in redistribution layer (RDL) design, particularly in achieving compactness and increased bonding strength due to spatial constraints and the need for RDLs to be spaced apart, which restricts the degree of freedom in RDL layout.
Innovation Solution
The design incorporates a second redistribution layer (RDL) that passes through the region where the first RDL is formed, with a passivation layer electrically isolating the two and under bump metal layers connecting them to solder bumps, allowing for increased design flexibility and bonding strength while maintaining electrical insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional RDL design with spaced-apart layers is used, then electrical insulation is maintained, but design freedom and compactness are restricted
Solution Approach 1:
A passivation layer is introduced as an intermediary between the first and second RDLs. This passivation layer provides electrical insulation while allowing the second RDL to be positioned directly over the first RDL, eliminating the need for lateral spacing and enabling more compact and flexible RDL designs.
2Volume of moving object
If RDLs are positioned closer together to improve compactness, then package size is reduced, but electrical insulation becomes compromised
Solution Approach 1:
The passivation layer serves as an electrical insulator positioned between the first and second RDLs, enabling them to be vertically stacked with minimal spacing. This maintains reliable electrical insulation while achieving compact package dimensions through vertical integration rather than lateral expansion.
3Adaptability or versatility
If second RDL passes through first RDL region, then design flexibility and bonding strength are improved, but manufacturing complexity increases
Solution Approach 1:
The second RDL is positioned in the vertical dimension directly over the first RDL rather than requiring lateral displacement. This vertical stacking approach, enabled by the passivation layer, allows the second RDL to pass through the region occupied by the first RDL in the plan view, improving design flexibility and bonding strength while maintaining manufacturability through standardized layering processes.
Data Source
AI summary
A semiconductor package with improved redistribution layer design and fabricating method thereof are disclosed and may include a semiconductor die comprising bond pads, a first redistribution layer (RDL) formed on the semiconductor die. The first RDL has a first end coupled to a bond pad and a second end coupled to a solder bump via under bump metal layers. A second RDL is formed in a same plane of the semiconductor die as the first RDL and is electrically isolated from the first RDL. A first end of the second RDL may be coupled to a bond pad and the second RDL may pass underneath, but be electrically isolated from, the solder bump. A passivation layer may be formed on the first and second RDLs exposing the second end of the first RDL. The under bump metal layers may be formed on the second end of the first RDL exposed by the passivation layer.