Redistribution Layer for Semiconductor Package Signal Integrity
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Solution Overview
Problem
Conventional semiconductor packages experience degradation of chip characteristics due to long bonding wires and limitations in power supply, especially for high-speed and high-performance chips with multiple aluminum bonding pads, leading to issues like warpage and copper ion migration.
Innovation Solution
A semiconductor package design featuring a redistribution layer with a stacked structure of seed metal and wiring metal layers, connected to bonding pads on a center pad type chip, with a substrate and solder bumps for improved power-ground characteristics and signal transmission, eliminating the need for multiple substrates and optimizing power pin interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect semiconductor chip with substrate, then electrical connection is achieved, but bonding wire length increases causing degradation of chip characteristics
Solution Approach 1:
A redistribution layer is introduced as an intermediary component between the bonding pads and the substrate. This redistribution layer redistributes the electrical connections, allowing shorter bonding wires to be used while maintaining proper electrical connectivity. The redistribution layer acts as a mediator that decouples the direct long-distance wire bonding requirement from the chip-substrate connection.
2Power
If multiple aluminum bonding pads are used on high-speed semiconductor chip, then power supply capability is improved, but package size increases causing inability to perform wire bonding for all pads
Solution Approach 1:
The redistribution layer utilizes the vertical dimension by stacking multiple metal layers (Cu/Ni/Au or Cu/Au) to achieve three-dimensional interconnection. This allows multiple bonding pads to be electrically connected through vertical vias and stacked conductive layers rather than requiring all pads to be distributed in a single plane, effectively reducing the package footprint while maintaining power supply capability.
3Area of stationary object
If power pin bonding option is used to reduce package size, then wire bonding feasibility is improved, but electric characteristics of package are degraded
Solution Approach 1:
The redistribution layer implements local quality optimization by providing different metal layer configurations for different functional requirements. Signal pads can access specific metal layers optimized for signal integrity, while power pins can access layers optimized for power delivery. This localized optimization maintains excellent electric characteristics for both signal and power connections within a compact package size.
4Adaptability or versatility
If multiple substrate is used to solve bonding pad connection problem, then connection capability is improved, but warpage and copper ion migration occur lowering package reliability
Solution Approach 1:
The redistribution layer combines multiple interconnection functions into a single integrated structure. Instead of using multiple separate substrates to achieve different connection functions, the redistribution layer integrates signal routing, power distribution, and ground connections within one unified multi-layer structure, eliminating the warpage and copper ion migration issues associated with multiple substrate stacking.
Data Source
AI summary
A high-speed and high-performance semiconductor package reduces degradation of chip characteristics when chips are packaged. The semiconductor package includes a semiconductor chip including a plurality of bonding pads, a redistribution layer formed on the semiconductor chip while being connected with the bonding pads, a substrate attached to an upper surface of the semiconductor chip and formed with a window for exposing the redistribution layer, a connection member for electrically connecting the bonding pad of the semiconductor chip with the substrate, a sealing member for sealing the window including the connection member and a surface of the substrate including the semiconductor chip, solder balls attached to the substrate.