Redistribution Layer Layout for Shorter Chip Signal Paths
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in data signal transmission and power consumption.
Innovation Solution
A semiconductor device design featuring a first chip with a plug structure and redistribution layer configuration that allows data signal transmission through bonding pads and redistribution layers without passing through conductive features, reducing transmission distance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data signal transmission path is shortened to reduce power consumption, then power consumption is reduced, but device complexity increases due to redistribution structure design
Solution Approach 1:
The patent introduces a redistribution layer structure that routes data signals in a different spatial dimension - specifically, creating separate transmission paths that bypass the plug structure vertically. The redistribution layer is positioned at a different height (Z-dimension) than the plug structure, allowing signals to travel horizontally through the redistribution layer rather than vertically through the plug, thus shortening the effective transmission distance while maintaining a systematic layout
Solution Approach 2:
The redistribution layer acts as an intermediary structure that mediates between the plug structure and the bonding pads. Instead of direct connection, the redistribution layer provides an intermediate routing path that allows data signals to bypass the plug structure, effectively reducing the transmission path length while maintaining electrical connectivity through a controlled intermediary route
2Speed
If signal transmission distance is reduced to improve performance, then transmission distance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the signal transmission path into distinct functional layers: the plug structure for vertical connectivity, the redistribution layer for horizontal routing, and bonding pads for external connections. This segmentation allows each layer to be optimized independently - the redistribution layer can be designed to provide short transmission paths for performance while the segmentation into separate manufacturing layers simplifies the overall fabrication process by allowing sequential formation of each component
3Reliability
If redistribution layer is positioned distant from plug structure to reduce interference, then signal interference is reduced, but device area increases
Solution Approach 1:
The patent resolves the area conflict by utilizing the vertical dimension (Z-axis) to separate the redistribution layer from the plug structure. Instead of increasing horizontal distance to reduce interference, the redistribution layer is positioned at a different height level, allowing close horizontal proximity (saving area) while maintaining vertical separation (reducing interference). This three-dimensional layering achieves both goals simultaneously
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.