Redistribution Layer for Stacked Semiconductor Chip Interconnects
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high-speed operation due to longer electrical connection paths between memory chips and logic chips, which complicates board routing and increases package size.
Innovation Solution
A semiconductor package design featuring a redistribution layer on the uppermost memory chip, connecting memory chips to a logic chip via conductive connections, and integrating passive devices like decoupling capacitors and buffer chips to reduce signal transfer paths and eliminate the need for board internal wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory chips are connected to logic chips via board internal wirings, then routing is simplified, but electrical connection path length increases and operation speed decreases
Solution Approach 1:
The patent transitions from planar board-level connections to three-dimensional stacked chip connections. Memory chips are vertically stacked above logic chips, with redistribution layers enabling electrical connections between chips in the stack. This vertical arrangement shortens signal paths and eliminates the need for long board internal wirings, thereby improving operation speed while managing complexity through systematic layer design.
Solution Approach 2:
Redistribution layers serve as intermediary structures between memory chips and logic chips. These layers contain conductive patterns that redirect and reorganize electrical signals, enabling direct inter-chip connections without requiring complex board routing. The redistribution layer acts as a mediator that simplifies the connection architecture while maintaining signal integrity.
2Area of stationary object
If chips are arranged to reduce package size, then integration density increases, but electrical connection paths become longer and more complex
Solution Approach 1:
The patent employs vertical stacking of chips to reduce the horizontal footprint of the package. Multiple memory chips are positioned above logic chips in a stacked configuration, utilizing the vertical dimension to achieve high integration density. This approach minimizes package area while keeping connection paths short and direct through the use of redistribution layers for inter-chip electrical connections.
3Speed
If direct chip-to-chip connections are implemented, then operation speed increases, but manufacturing and alignment precision requirements increase
Solution Approach 1:
Redistribution layers function as intermediary structures that facilitate precise electrical connections between stacked chips. These layers include conductive patterns and pads that are carefully designed to align with corresponding elements on adjacent chips. The redistribution layer absorbs and compensates for minor alignment variations, enabling direct chip-to-chip connections while managing manufacturing precision requirements.
Solution Approach 2:
The connection architecture is segmented into multiple functional layers including redistribution layers, conductive connections, and chip interfaces. This segmentation allows each layer to be optimized independently for its specific function, with redistribution layers handling signal routing and alignment tolerance, thereby reducing the overall manufacturing precision burden while maintaining high-speed direct connections.
Data Source
AI summary
Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second semiconductor chip that are stacked sequentially on a board. The semiconductor packages may also include a wiring layer on the memory chips and the wiring layer may include redistribution patterns and redistribution pads. Each of the memory chips may include a data pad. The data pads of the first semiconductor chips may be electrically connected to the board via the second semiconductor chip, some of redistribution patterns, and some of redistribution pads.