Redistribution Layer Wiring-Free Zones for 3DIC Stress Relief
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Solution Overview
Problem
Current semiconductor packaging methods face challenges in efficiently routing and interconnecting semiconductor dies due to limitations in conductive routing structures, leading to issues with thermal stress and reliability, particularly in three-dimensional integrated circuit (3DIC) devices.
Innovation Solution
The implementation of a redistribution layer with wiring-free zones, which are metal-free dielectric blocks, is used to form a semiconductor package structure. This layer includes alternating dielectric and conductive layers, with wiring-free zones defined by forming multiple dielectric layers without metallization patterns, allowing for efficient die attachment and stress relief through dielectric material buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive routing structures are used to interconnect semiconductor dies, then electrical connections are established, but thermal stress and reliability issues arise
Solution Approach 1:
The redistribution layer is segmented into conductive regions with metallization patterns and wiring-free zones without metallization. This segmentation allows the structure to simultaneously provide electrical connections in conductive regions and stress relief in wiring-free zones, resolving the contradiction between establishing electrical connections and reducing thermal stress.
Solution Approach 2:
Different regions of the redistribution layer are assigned different properties: conductive regions have metallization patterns for electrical connectivity, while wiring-free zones have only dielectric material for stress relief. This local differentiation allows each region to optimize its function, reducing overall thermal stress while maintaining necessary electrical connections.
2Stress or pressure
If wiring-free zones are added to the redistribution layer, then thermal stress is reduced, but device complexity increases
Solution Approach 1:
The redistribution layer is divided into standard conductive regions and wiring-free zones using the same dielectric layering process. This segmentation approach integrates stress relief functionality into the existing manufacturing workflow without requiring entirely new process steps, thereby limiting the increase in device complexity.
Solution Approach 2:
The dielectric layers in the redistribution layer serve multiple functions: they provide electrical insulation in conductive regions and form the structural basis of wiring-free zones for stress relief. This multi-functionality reduces the need for additional specialized components, limiting complexity increase.
3Reliability
If metallization patterns are removed to create wiring-free zones, then underfill cracking is reduced, but electrical connection density decreases
Solution Approach 1:
Metallization patterns are selectively removed only in wiring-free zones located at specific regions of the redistribution layer, while conductive regions maintain full metallization. This local quality differentiation preserves electrical connection density in critical areas while providing underfill cracking resistance in regions where electrical connections are less critical.
Solution Approach 2:
The redistribution layer is segmented into conductive regions with metallization and wiring-free zones without metallization. This segmentation allows the structure to simultaneously provide electrical connections in conductive regions and stress relief in wiring-free zones, resolving the contradiction between establishing electrical connections and reducing thermal stress.
Data Source
AI summary
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has a semiconductor die and a redistribution layer disposed on an active surface of the semiconductor die and electrically connected with the semiconductor die. The redistribution layer has a wiring-free zone arranged at a location below a corner of the semiconductor die. An underfill is disposed between the semiconductor die and the redistribution layer. The wiring-free zone is located below the underfill and is in contact with the underfill. The wiring-free zone extends horizontally from the semiconductor die to the underfill.