Redistribution Layer Plate Formation Using Temporary Bond Pad Plugs
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Solution Overview
Problem
Current fan-out wafer level packaging (FOWLP) and panel-level packaging (PLP) processes require multiple steps and complex equipment sets to form connections between die bond pads and redistribution layers, particularly for wafer diameters greater than eight inches, which is inefficient and not scalable for smaller chip-size electronic packages.
Innovation Solution
A method involving the deposition of temporary plugs on bond pads, encapsulation with a mold compound, and removal of plug portions to create openings for a unitary redistribution layer plate that extends through the mold compound and is in electrical communication with the bond pad, simplifying the process and reducing equipment requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-step processes are used to form connections between die bond pads and redistribution layers, then connection reliability is achieved, but the number of manufacturing steps and equipment complexity increases
Solution Approach 1:
The patent combines multiple separate manufacturing steps into a single integrated process. Specifically, the mold compound is applied in one step that simultaneously encapsulates the die, forms the compound layer, and creates the recessed region for the redistribution layer plate, eliminating the need for separate molding, planarization, and recess formation steps required by traditional processes
Solution Approach 2:
The patent performs preliminary actions by forming the recessed region within the mold compound during the initial molding step, before the redistribution layer plate is deposited. This preliminary formation of the recessed region eliminates the need for subsequent grinding or planarization steps to create the necessary accommodation space for the redistribution layer plate
2Adaptability or versatility
If traditional processes support wafer diameters greater than or equal to eight inches, then manufacturing capability is maintained, but scalability to smaller chip-size packages is limited
Solution Approach 1:
The patent creates a universal manufacturing process that can handle multiple wafer sizes and package types through a single methodology. The mold compound-based approach with integrated recess formation works equally well for large eight-inch wafers and smaller chip-size packages, eliminating the need for different process configurations or specialized equipment for different wafer dimensions
Solution Approach 2:
The patent segments the manufacturing process into distinct functional stages: die preparation with bond pads, single-step mold compound application that simultaneously performs encapsulation and recess formation, and redistribution layer plate deposition. This segmentation allows each stage to be optimized independently and scaled to different wafer sizes without affecting other stages
3Manufacturing precision
If multiple separate steps are used for molding, planarization, and redistribution layer deposition, then manufacturing precision is maintained, but manufacturing time and cost increase
Solution Approach 1:
The patent merges the molding step with the recess formation step into a single mold compound application process. The mold compound is applied in one operation that simultaneously encapsulates the die and creates the precise recessed region, eliminating the time required for separate planarization and recess formation operations while maintaining the dimensional precision needed for subsequent redistribution layer plate deposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of steps and simplifies the equipment needed, enabling the efficient manufacture of chip-size electronic packages with a unitary redistribution layer plate in contact with the bond pad, improving scalability and manufacturing efficiency for smaller wafer diameters.
Implementation Method 1
encapsulating the proximal end of the first plug and at least a portion of the die proximate the proximal end of the first plug with a mold compound
Implementation Method 2
depositing a first redistribution layer plate on a portion of the mold compound and in the first opening in the mold compound on the first bond pad
Data Source
AI summary
Electronic packages comprising: a die with a bond pad, a mold compound encapsulating at least exposed surfaces of the die surrounding the bond pad, and a unitary redistribution layer plate on at least a portion of the mold compound and extending through the mold compound in electrical communication with the bond pad. A method comprising: depositing a plug on a die bond pad, encapsulating a proximal end of the plug and at least a portion of the die proximate the proximal end of the plug with a mold compound, removing the plug from the bond pad to form an opening in the mold compound, and depositing a redistribution layer plate on the mold compound and in the opening in the mold compound on the bond pad.