Redistribution-Layer Semiconductor Package for Thin Multi-Chip Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages face challenges in miniaturization and increased capacity due to the need for larger spaces for stacking and mounting multiple semiconductor chips, which limits their performance and efficiency in compact electronic devices.
Innovation Solution
A semiconductor package design featuring a redistribution layer with multiple redistribution patterns and conductive vias that connects multiple semiconductor chips side-by-side, allowing for direct electrical contact and reduced thickness through the use of a molding layer and a land grid array substrate, enabling efficient signal and heat transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked or mounted side-by-side on a package substrate, then storage capacity and functionality are increased, but the package size and vertical thickness increase
Solution Approach 1:
The patent transitions from vertical stacking to horizontal side-by-side mounting of semiconductor chips on the package substrate. The redistribution layer extends horizontally to provide electrical connections to multiple chips mounted in the same plane, reducing vertical thickness while maintaining increased storage capacity through parallel chip arrangement.
Solution Approach 2:
The package substrate is divided into multiple mounting regions with separate chip mounting areas. The redistribution layer is segmented into multiple redistribution patterns, each serving a specific chip, allowing independent mounting and connection of multiple semiconductor chips in a distributed horizontal layout.
2Device complexity
If multiple semiconductor chips are mounted side-by-side with horizontal spacing, then electrical connectivity is simplified, but the package area increases
Solution Approach 1:
The redistribution layer serves multiple functions simultaneously: it provides electrical connections to multiple horizontally-spaced chips, acts as a structural interconnection network, and enables signal distribution across the package. This multi-functional design allows simplified connectivity architecture without requiring proportional area increase.
Solution Approach 2:
The redistribution patterns are designed with optimized trace widths, spacing, and routing densities to maintain electrical performance while minimizing area occupation. By adjusting geometric parameters of the redistribution layer, the patent achieves efficient connectivity with reduced area overhead from horizontal chip spacing.
3Area of stationary object
If chips are mounted closer together to reduce area, then heat dissipation becomes more difficult, but space utilization improves
Solution Approach 1:
The package substrate incorporates localized thermal management features such as heat sinks, thermal vias, or heat spreaders positioned near individual chip mounting regions. This allows targeted heat dissipation at high-heat-generation locations while maintaining close chip spacing for space efficiency, addressing thermal concerns locally without increasing overall package area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for high-performance semiconductor packages to be integrated in smaller spaces, reducing vertical thickness and enhancing heat dissipation while maintaining efficient electrical connectivity.
Implementation Method 1
at least some of the plurality of redistribution patterns of the redistribution layer are in direct contact with and electrically connected to the plurality of first lower surface pads of the sub-semiconductor package, respectively
Implementation Method 2
enhancing heat dissipation while maintaining efficient electrical connectivity
Data Source
AI summary
A semiconductor package includes: a redistribution layer including a plurality of redistribution patterns; a sub-semiconductor package including a sub-semiconductor package substrate and a first semiconductor chip that is on the sub-semiconductor package substrate, wherein the sub-semiconductor package substrate is on the redistribution layer and includes a plurality of first lower surface pads; and a second semiconductor chip on the redistribution layer and spaced apart from the sub-semiconductor package in a horizontal direction, wherein the second semiconductor chip includes a chip pad, wherein at least some of the plurality of redistribution patterns of the redistribution layer are overlapped with and electrically connected to the plurality of first lower surface pads of the sub-semiconductor package, respectively.