Redistribution Layer Packaging With Two-Step Cutting for Dielectric Integrity

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Solution Overview

Problem

The fragility of low dielectric constant material layers in electronic devices makes them prone to chipping or cracking during the cutting process, compromising the structural stability and reliability of the devices.

Innovation Solution

A manufacturing method involving two distinct cutting steps with different conditions is employed, where a first cutting step with milder conditions is used to cut the protection layer and insulation layers, and a second cutting step with more aggressive conditions is used to cut the substrate layer, reducing the risk of chipping or cracking and enhancing the bonding quality between layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single aggressive cutting step is used to cut through all layers including the substrate, then cutting efficiency is improved, but the low dielectric constant material layer is prone to chipping or cracking

Engineering Contradiction:
Improvecutting efficiencyVSAvoidintegrity of dielectric layer
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The cutting process is divided into two distinct steps: a first cutting step that cuts through the protection layer and low dielectric constant material layer with milder conditions, and a second cutting step that cuts the substrate layer with more aggressive conditions. This segmentation allows each cutting step to be optimized for its specific material, preventing damage to the fragile dielectric layer while maintaining overall cutting efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cutting parameters (such as cutting speed, depth, and aggressiveness) are changed between two distinct cutting steps. The first cutting step uses milder parameters suitable for the fragile low dielectric constant material layer, while the second cutting step uses more aggressive parameters appropriate for the substrate layer, thereby preventing chipping or cracking while maintaining productivity.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a single cutting condition is used for all layers, then process complexity is reduced, but the fragile dielectric layer suffers damage

Engineering Contradiction:
Improvecutting process complexityVSAvoidquality of cut surfaces
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The cutting process is segmented into two distinct steps with different conditions: a first cutting step for the protection layer and dielectric layer, and a second cutting step for the substrate layer. This segmentation ensures that each layer is cut under optimal conditions, maintaining high manufacturing precision while managing process complexity through a systematic approach.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different cutting conditions are applied to different regions/layers of the workpiece. The first cutting step uses milder conditions localized to the protection and dielectric layers, while the second cutting step uses aggressive conditions localized to the substrate layer. This local quality approach ensures each layer receives the appropriate cutting treatment for optimal results.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240404831A1Electronic device and manufacturing method thereof
Publication Date: 2024.12.05 INNOLUX CORP
  • US20240404831A1 patent drawing
  • US20240404831A1 patent drawing
  • US20240404831A1 patent drawing

AI summary

An electronic device includes a chip, a protection, a molding layer and a redistribution structure layer. The chip has an active surface and a first side surface connected to the active surface. The protection layer is disposed on the active surface of the chip and has a second side surface. The molding layer surrounds the chip and the protection layer. The redistribution structure layer is disposed on the molding layer, on the protection layer and electrically connected to the chip. The roughness of the first side surface is different from the roughness of the second side surface.