Semiconductor Package Redistribution Layer Undulation Control
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Solution Overview
Problem
In semiconductor packaging, existing technologies face challenges in controlling undulation and ensuring reliable insulation in redistribution layers, particularly due to thickness deviations and voids caused by foreign matter and insufficient filling of non-photosensitive insulation layers, which can lead to defects and reduced fine pitch capabilities.
Innovation Solution
A semiconductor package design that includes a first redistribution layer with openings having a cross-shaped protrusion structure, where the thickness of the first redistribution layer is 10 μm or less, and a second insulation layer covering the first redistribution layer, with a thickness ratio of B/A being 1.5 or less, to improve interlayer adhesion and reduce undulation phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a non-photosensitive insulation layer is used in the redistribution layer formation, then the manufacturing process is simplified, but fine pitch capability is limited and undulation control becomes difficult
Solution Approach 1:
The patent changes the material parameter of the insulation layer from non-photosensitive to photosensitive material, enabling precise pattern formation through photolithography. This allows for fine pitch redistribution layers with controlled dimensions and better undulation management, while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
2Volume of moving object
If the redistribution layer thickness is reduced for fine design, then the package size is minimized, but undulation control becomes more difficult and insulation reliability decreases
Solution Approach 1:
The patent optimizes the thickness parameter of the photosensitive insulation layer to a specific range that provides sufficient insulation reliability while maintaining fine design capabilities. The photosensitive material properties enable precise thickness control through photolithographic processing, ensuring reliable insulation even at reduced thicknesses required for miniaturized packages.
3Manufacturing precision
If vacuum lamination method is used for insulation layer formation, then thickness deviation is compensated, but foreign matter contamination and void formation increase
Solution Approach 1:
The patent replaces the mechanical vacuum lamination process with a photolithographic patterning process for insulation layer formation. This substitution eliminates the need for high-pressure lamination that can trap foreign matter and create voids, while achieving superior thickness uniformity and pattern precision through photoresist coating and development processes.
Data Source
AI summary
This invention provides a semiconductor package, the semiconductor package includes: a semiconductor chip having a connection pad; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the semiconductor chip and the encapsulant. The connection structure comprises a first insulation layer, a first redistribution layer disposed on the first insulation layer, and a second insulation layer disposed on the first insulation layer and covering the first redistribution layer. The first redistribution layer has one or more openings. The openings have a shape having a plurality of protrusions, respectively, and B/A is 1.5 or less, where A refers to a thickness of the first redistribution layer, and B refers to a thickness of a region of the second insulation layer covering the first redistribution layer.