Semiconductor Redistribution Layer Via Geometry Optimization
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Solution Overview
Problem
Current semiconductor package redistribution layers face challenges in achieving high-density circuit layouts due to the design of vias, which are larger than needed, leading to inefficient electrical conduction and space utilization.
Innovation Solution
The redistribution layer design incorporates vias with smaller cross-sectional widths and optimized pitch-to-width ratios, allowing for better conductive wire utilization and improved electrical connectivity by using a dielectric layer with specific thickness and conductive wire configurations, including upper and lower conductive wires separated by the dielectric layer, with vias penetrating to connect them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are designed with larger cross-sectional areas to improve electrical transmission, then electrical conduction ability is improved, but circuit layout density deteriorates
Solution Approach 1:
The patent changes the geometric parameters of vias by controlling the ratio of via cross-sectional width to dielectric layer thickness to be less than or equal to 1, and optimizing the pitch-to-width ratio to be greater than or equal to 0.5. This parameter optimization allows vias to achieve sufficient electrical conduction while minimizing their cross-sectional area, thereby improving circuit layout density without sacrificing electrical transmission performance.
2Area of stationary object
If via cross-sectional width is reduced to increase circuit density, then area utilization is improved, but electrical conduction ability deteriorates
Solution Approach 1:
The patent identifies optimal parameter ranges for via dimensions: the via cross-sectional width to dielectric layer thickness ratio is controlled at ≤1, and the pitch between adjacent vias to via width ratio is controlled at ≥0.5. These parameter changes ensure that even with reduced via dimensions for higher density, the electrical conduction ability is maintained at acceptable levels through optimized geometric proportions.
3Area of stationary object
If via dimensions are optimized for high density, then manufacturing precision requirements increase
Solution Approach 1:
The patent establishes specific parameter ranges (via width/thickness ratio ≤1, pitch/width ratio ≥0.5) that provide design margins for manufacturing variability. By optimizing within these ranges rather than pushing to extreme limits, the patent achieves high via density while maintaining manufacturability and controlling precision requirements at practical levels.
Data Source
AI summary
A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.