Redistribution Layer Via Plug Shapes for FO-WLP Step Differences
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Solution Overview
Problem
Conventional fan-out wafer level packages (FO-WLP) face defects and bonding failures due to step differences in the redistribution layer, which hinder the formation of fine line widths and stable connections between semiconductor chips and external connection terminals.
Innovation Solution
A semiconductor package with a redistribution layer featuring an upper pad and fine pattern formed on a support substrate, minimizing step differences and defects, and including via plugs with specific cross-sectional shapes to ensure stable bonding and reduced defects during the exposure process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional redistribution layer is formed in FO-WLP, then the package structure is completed, but step differences occur causing bonding failures and defects
Solution Approach 1:
The patent introduces a vertical dimension solution by forming via plugs with specific cross-sectional shapes (trapezoidal, inverted trapezoidal, or rounded bottom) to compensate for step differences. This dimensional approach allows the via plugs to bridge height variations between different redistribution layer levels, enabling stable bonding despite manufacturing step differences.
Solution Approach 2:
The patent changes the geometric parameters of the via plugs by specifying different cross-sectional shapes (trapezoidal, inverted trapezoidal, rounded bottom) and width variations at different heights. These parameter changes allow the via plugs to adapt to varying step heights and ensure reliable electrical connection and mechanical bonding stability.
2Manufacturing precision
If fine line widths are required in the redistribution layer, then the pattern precision is improved, but step differences cause exposure process defects
Solution Approach 1:
The patent performs preliminary action by pre-forming the via plugs with optimized cross-sectional shapes before the final exposure process. This preliminary structuring of the via plugs compensates for potential step differences, creating a stable foundation that allows subsequent fine line width patterning to proceed without exposure process defects.
Solution Approach 2:
The patent changes the geometric parameters of via plugs to have wider widths at certain heights (trapezoidal or inverted trapezoidal shapes), which provides a broader base for fine line width patterns. This parameter adjustment ensures that the exposure process can accurately form fine lines without being disrupted by underlying step differences.
3Length of moving object
If the overall thickness of the semiconductor package is decreased for miniaturization, then the package size is reduced, but the redistribution layer structure becomes more complex
Solution Approach 1:
The patent segments the redistribution layer into multiple units, each containing a via plug with a specific cross-sectional shape. This segmentation allows the complex redistribution function to be divided into manageable modular units, making the overall structure more controllable and manufacturable despite the reduced package thickness.
Solution Approach 2:
The patent applies local quality by giving different via plugs different cross-sectional shapes (trapezoidal, inverted trapezoidal, rounded bottom) depending on their specific location and function within the redistribution layer. This localized optimization allows the structure to handle complexity efficiently while maintaining overall compactness.
Data Source
AI summary
Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.