Redistribution Layer for Wafer-Level Chip Scale Package

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Solution Overview

Problem

The existing wafer-level chip-scale packaging process faces challenges in preventing undesirable etching in regions with step coverage, which can lead to open connections between bond pads and metal traces, reducing the reliability of packaged IC devices.

Innovation Solution

A method is introduced where a photo resist is used as an etch barrier to protect the metal layers at bond and bump pads, ensuring that only the top metal layer is etched away, leaving the bottom metal layer intact to maintain connections between bond and bump pads, thereby preventing over-etching and enhancing reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple metal layers are deposited to improve adhesion and conductivity, then the reliability of the packaging is enhanced, but the complexity of the manufacturing process increases

Engineering Contradiction:

Improvepackaging reliabilityVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The metal interconnect structure is divided into multiple functional layers: bottom metal layer (Al/NiV/Cu/Ti) for adhesion and mechanical strength, and top metal layer (NiV/Cu) for conductivity and solder wetting. This segmentation allows each layer to be optimized for its specific function while simplifying the overall manufacturing process by enabling selective etching of the top layer without affecting the bottom layer

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The photo resist is applied as a protective barrier before the etching process begins. This preliminary protective action prevents over-etching of the bottom metal layer during subsequent manufacturing steps, ensuring that the adhesion layer remains intact while allowing selective removal of the top metal layer

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the top metal layer is etched away to define connection traces, then the electrical conductivity is improved, but the risk of over-etching and open connections increases

Engineering Contradiction:

Improveconnection reliabilityVSAvoidetching precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The photo resist serves as an intermediary protective layer between the etching chemistry and the metal layers. It is applied as a positive tone photo resist that is insoluble in the etching solution, creating a physical barrier that prevents etching of the bottom metal layer while allowing selective etching of the top metal layer through defined openings

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The bottom metal layer (Al/NiV/Cu/Ti) is designed with sufficient thickness and strong adhesion properties to serve as a cushioning reserve that prevents complete trace failure even if some etching occurs. The Ti layer specifically provides a diffusion barrier and mechanical strength cushion against over-etching damage

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents over-etching at step coverage areas, ensuring reliable connections between bond and bump pads, thereby increasing the electrical yield and reliability of packaged IC devices.

Implementation Method 1

a photo resist is used as an etch barrier to protect the metal layers at bond and bump pads

Methodology Applied

Scientific EffectEtch barrier:

Implementation Method 2

Multiple metal layers of different metals and alloys, such as Al, NiV, Cu, Ti, NiV, and Cu, are deposited on the surfaces

Methodology Applied

Scientific EffectMetal layer deposition: Deposition (physical)

Implementation Method 3

aluminum may be sputtered onto the silicon substrate, followed by a sputtering of layers of nickel-vanadium

Methodology Applied

Scientific EffectSputtering: Sputtering

Data Source

PatentEP1941541B1Redistribution layer for wafer-level chip scale package and method therefor

Publication Date: 2012.03.28 SEONG CAPITAL LTD LIMITED LIABILITY

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AI summary

In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first dielectric layer (315) and filling (20) in bond pad openings (310) and bump pad openings (330); the metal layer (360) has a top (340) and bottom (360) layer. In the metal layer (360), bond pad connections (310) and bump pad connections (330) are defined (25, 30) by removing the top layer of metal in areas other than at bond pad openings (310) and bump pad openings (330), and leaving the bottom layer (360) of metal in areas without bond pad or bump pad connections. In the bottom metal layer, connection traces between the bond pad and bump pad are defined (35, 40). A second organic dielectric layer (325) is deposited (45) on the silicon substrate (305), enveloping the circuit pattern. The second organic dielectric layer is removed (50) from the bump pad connections exposing the bump pads (330).