Redistribution Structure Layout for Low-Capacitance Chip I/O
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Solution Overview
Problem
Existing semiconductor packages face challenges in maintaining input/output reliability and suppressing parasitic capacitance in the upper redistribution structure, which affects the performance and efficiency of the package.
Innovation Solution
The semiconductor package incorporates a lower redistribution structure with a lower semiconductor chip, an upper redistribution structure featuring a signal pad, power pad, grounding plane, and upper insulation layer, where the signal pad is positioned closer to the lower redistribution structure than the power pad, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the signal pad is positioned closer to the lower redistribution structure, then parasitic capacitance is reduced, but signal interference from power/grounding planes may increase
Solution Approach 1:
The upper redistribution structure is divided into distinct functional regions: a first region containing the grounding plane and a second region containing the signal pad. This spatial segmentation separates signal and power/ground paths, reducing parasitic capacitance while preventing signal interference through regional isolation.
Solution Approach 2:
Different regions of the upper redistribution structure are assigned different functional qualities: the first region is optimized for grounding with continuous plane structure, while the second region is optimized for signal transmission with controlled impedance. This local differentiation allows each region to perform its function optimally without interfering with the other.
2Weight of moving object
If the upper semiconductor chip is made thinner to reduce package weight, then weight is reduced, but input/output reliability may deteriorate
Solution Approach 1:
The redistribution structures are designed with multi-layer configurations in the vertical dimension, with signal pads, power pads, and grounding planes distributed across different layers. This three-dimensional arrangement allows for optimized signal paths and reduced parasitic effects without increasing the horizontal footprint or compromising reliability, enabling thinner chip designs.
3Adaptability or versatility
If multiple semiconductor chips with various functions are integrated in a single package, then functionality is enhanced, but device complexity increases
Solution Approach 1:
The upper redistribution structure is designed as a multi-functional platform that simultaneously supports signal transmission, power distribution, and grounding functions through its differentiated regions. This universal design allows various semiconductor chips with different functions to be integrated into a single package while maintaining organized and manageable interconnections, reducing overall system complexity.
Data Source
AI summary
A semiconductor package includes a lower redistribution structure, a lower semiconductor chip on the lower redistribution structure, and an upper redistribution structure t on the lower semiconductor chip and including a signal pad, a power pad, a grounding plane, and an upper insulation layer, where the signal pad, the power pad, and the grounding plane are in the upper insulation layer, where a distance between the signal pad and the lower redistribution structure in a vertical direction is less than a distance between the power pad and the lower redistribution structure in the vertical direction, and where the vertical direction is perpendicular to an upper surface of the lower redistribution structure.