Redistribution Structure Layout for Thermal Stress Relief in Packages
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Solution Overview
Problem
The coefficient of thermal expansion (CTE) mismatch between semiconductor devices and substrates in semiconductor packages leads to thermal stress on redistribution structures, particularly during thermal cycling, causing stress on redistribution lines and potentially leading to cracking.
Innovation Solution
Incorporating a redistribution structure with vias and conductive lines that form an angle greater than zero between adjacent lines, and additional dielectric layers to provide flexibility, which helps to release thermal stress and increase the reliability of the redistribution lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If redistribution lines are arranged in parallel configuration, then manufacturing is simplified, but thermal stress concentration increases leading to cracking
Solution Approach 1:
The patent applies asymmetry by arranging conductive lines at non-parallel angles (e.g., 45 degrees) instead of in parallel configuration. This asymmetric angular arrangement allows differential thermal expansion between adjacent lines, preventing stress concentration and cracking while maintaining manufacturing feasibility through standardized photolithography processes.
Solution Approach 2:
The patent introduces dynamic flexibility by forming conductive lines with curved or meandering paths rather than straight parallel lines. This dynamic geometry allows the conductive lines to flex and accommodate thermal expansion differences between the semiconductor device and substrate, reducing stress concentration during thermal cycling.
2Stability of the object's composition
If rigid redistribution structure is used, then structural stability is improved, but thermal stress leads to cracking
Solution Approach 1:
The patent employs flexible dielectric layers (e.g., polyimide) as encapsulating materials that can flex and accommodate thermal expansion differences. These flexible thin films maintain structural stability while allowing the redistribution structure to adapt to thermal stress, preventing crack formation in rigid components.
Solution Approach 2:
The patent segments the redistribution structure into multiple conductive lines at different angles and positions. This segmentation distributes thermal stress across multiple independent pathways rather than concentrating it in a single rigid structure, enhancing overall reliability while maintaining structural stability.
3Reliability
If conductive lines are arranged at angles, then thermal stress is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent changes the geometric parameter of conductive lines from parallel (0 degrees) to angled configurations (e.g., 45 degrees). This parameter change reduces thermal stress by allowing differential expansion while maintaining manufacturability through standard photolithography angle capabilities and simplified routing rules.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement reduces thermal stress on redistribution lines by allowing stress to distribute through the vias and conductive lines, enhancing the reliability and reducing stress levels by up to 10% compared to parallel configurations.
Implementation Method 1
The coefficient of thermal expansion (CTE) mismatch between semiconductor devices and substrates in semiconductor packages leads to thermal stress on redistribution structures, particularly during thermal cycling
Implementation Method 2
additional dielectric layers to provide flexibility, which helps to release thermal stress
Data Source
AI summary
A manufacturing method of a semiconductor package includes the following steps. A redistribution structure is formed. An encapsulated semiconductor device is provided on a first side of the redistribution structure, wherein the encapsulated semiconductor device comprising a semiconductor device encapsulated by an encapsulating material. A substrate is bonded to a second side of the redistribution structure opposite to the first side. The redistribution structure includes a plurality of vias connected to one another through a plurality of conductive lines and a redistribution line connected to the plurality of vias, and, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines.