Redistribution Line Profile for Delamination-Resistant Semiconductor Packages
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Solution Overview
Problem
Semiconductor packages face challenges in maintaining structural reliability due to complex redistribution patterns with decreasing size and distance, leading to issues such as delamination and electromigration.
Innovation Solution
A semiconductor package design featuring a redistribution line pattern with a lower portion having a horizontal length increasing downwards, a concave middle portion, and a convex upper portion, enhancing adhesion and dispersing stress through a specific manufacturing process involving a photoresist layer exposure and plating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the redistribution pattern size is decreased and distance between patterns is reduced to increase storage capacity, then the storage capacity increases, but the structural reliability deteriorates due to delamination and electromigration
Solution Approach 1:
The redistribution line pattern is designed with varying cross-sectional areas along its length, creating local quality variations. The cross-sectional area is larger at portions closer to the semiconductor chip and smaller at portions farther away, optimizing both adhesion strength and current carrying capacity at different locations to prevent delamination and electromigration while maintaining high storage capacity
Solution Approach 2:
The patent changes the geometric parameters of the redistribution line pattern by varying the cross-sectional area along its length. This parameter variation allows the structure to handle different mechanical and electrical stresses at different locations, improving overall reliability while maintaining the high-density layout required for increased storage capacity
2Quantity of substance
If the redistribution pattern size is decreased to increase storage capacity, then the storage capacity increases, but the adhesion to insulating layer deteriorates leading to delamination
Solution Approach 1:
The redistribution line pattern incorporates local quality variations with larger cross-sectional areas at specific portions to enhance adhesion strength where it is most needed, while maintaining smaller cross-sections in other areas to achieve high storage capacity
Solution Approach 2:
The patent employs a composite structure where the redistribution line pattern integrates multiple material layers with different properties. This composite approach enhances adhesion to the insulating layer while maintaining the electrical and mechanical performance required for high-density storage
3Quantity of substance
If the redistribution pattern size is decreased to increase storage capacity, then the storage capacity increases, but the electromigration resistance deteriorates
Solution Approach 1:
The redistribution line pattern is designed with locally varied cross-sectional areas that are optimized for current carrying capacity. Larger cross-sections are positioned where current density is highest to prevent electromigration, while smaller sections are used where less current flows, enabling high storage capacity without compromising electromigration resistance
Solution Approach 2:
The patent varies the cross-sectional area parameter along the length of the redistribution line pattern to optimize electromigration resistance. This parameter change ensures adequate current carrying capacity in high-stress regions while maintaining the compact design needed for high storage capacity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design increases structural reliability by improving adhesion to the insulating layer, reducing delamination, and enhancing electromigration resistance.
Implementation Method 1
exposing the photoresist layer such that an amount of hardening of a middle portion of the photoresist layer is greater than an amount of hardening of an upper portion of the photoresist layer and an amount of hardening of a lower portion of the photoresist layer
Implementation Method 2
forming a redistribution pattern by filling the via pattern hole of the insulating layer and the plurality of line pattern holes of the photoresist pattern
Data Source
AI summary
A method of manufacturing a semiconductor package includes forming an insulating layer; forming a seed layer on the insulating layer; forming a photoresist layer on the seed layer; forming a plurality of line pattern holes by patterning the photoresist layer, a horizontal length of a middle portion of each of the plurality of line pattern holes being less than a horizontal length of an upper portion of each of the plurality of line pattern holes and a horizontal length of a lower portion of each of the plurality of line pattern holes; and forming a redistribution line pattern by performing a plating process using a portion of the seed layer exposed by the plurality of line pattern holes.