Redistribution Structure Lithography for Fine-Pitch Wafer Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in forming redistribution structures for semiconductor packages with fine pitches and high integration density, as existing methods suffer from overlay shift issues and stitching between multiple exposures, which hinder the formation of smaller and more complex packaging techniques.
Innovation Solution
The method involves forming dielectric layers and metallization patterns using an aligner to expose the entire surface of the semiconductor wafer simultaneously, eliminating the need for multiple exposures and stitching, and planarizing each layer to improve the degree of planarization, allowing for the creation of redistribution structures with finer pitches and reduced overlay shift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple exposures and stitching are used to form redistribution structures, then coverage of the entire wafer surface is achieved, but overlay shift and stitching defects occur reducing manufacturing precision
Solution Approach 1:
The patent merges multiple exposure steps into a single exposure operation by using an aligner that can expose the entire wafer surface simultaneously. This combines what were previously separate stitching operations into one unified process, eliminating the overlay shift and stitching defects that arose from multiple sequential exposures.
Solution Approach 2:
The invention transitions from a sequential, step-by-step exposure approach (one dimension of time) to a simultaneous full-wafer exposure approach (adding the dimension of parallel processing). This dimensional change in the exposure process allows the entire redistribution structure to be formed in one operation rather than through multiple stitched exposures.
2Quantity of substance
If fine pitch features are formed in redistribution structures, then integration density increases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
By combining all exposure operations into a single simultaneous exposure step, the patent eliminates cumulative overlay errors that would otherwise accumulate through multiple exposures. This is critical for maintaining precision when forming fine pitch features, as even small errors in each step would compound and prevent achieving the required integration density.
3Manufacturing precision
If dielectric layers are planarized to improve surface flatness, then subsequent lithography precision improves, but process complexity increases
Solution Approach 1:
The patent performs planarization of dielectric layers as a preliminary action before the single simultaneous exposure step. By ensuring the surface is properly planarized beforehand, the subsequent lithography can achieve high precision in forming fine pitch features without requiring additional corrective steps, thus improving precision while managing process complexity.
Data Source
AI summary
A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.