Redistribution Package Structure With Controlled Carrier Debonding
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Solution Overview
Problem
Current wafer-level packaging technologies face challenges in efficiently integrating and testing semiconductor dies with high yield and cost-effectiveness, particularly in forming reliable redistribution circuit structures and ensuring proper debonding from carriers.
Innovation Solution
The method involves using a debond layer, such as a dielectric material like benzocyclobutene or epoxy-based thermal-release materials, on a carrier, followed by the formation of a redistribution circuit structure with alternating dielectric and metallization layers, through vias, and encapsulation, allowing for stable adhesion and easy debonding, and incorporating seed layers and conductive patterns for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level packaging is used to integrate semiconductor dies, then productivity and cost-effectiveness are improved, but achieving high yield and reliable electrical connectivity becomes difficult
Solution Approach 1:
The packaging process is segmented into distinct stages: forming redistribution circuit structures on the carrier, bonding semiconductor dies to the carrier, and then debonding the completed packages from the carrier. This segmentation allows each stage to be optimized independently, maintaining high productivity while ensuring reliable electrical connectivity through proper redistribution layer formation and bonding processes.
Solution Approach 2:
Redistribution circuit structures are formed on the carrier substrate before bonding the semiconductor dies. This preliminary action ensures that electrical connectivity pathways are established in advance, allowing for reliable signal routing from the die pads through the redistribution layers to the external contacts, thereby improving yield and connectivity reliability.
2Productivity
If semiconductor dies are bonded to carrier at wafer level, then manufacturing efficiency is improved, but debonding process becomes complex and yield-reducing
Solution Approach 1:
A carrier substrate serves as an intermediary that temporarily holds multiple semiconductor dies during the packaging process. The carrier enables wafer-level bonding operations to be performed efficiently, and after the packages are formed, the carrier can be debonded in a controlled manner. This intermediary approach simplifies the overall process by separating the bonding function from the final package handling.
3Reliability
If redistribution circuit structures are formed on carrier, then electrical connectivity is improved, but adhesion stability and debonding control become challenging
Solution Approach 1:
Different regions of the carrier substrate have different functional properties: regions with redistribution circuit structures provide electrical connectivity, while other regions maintain adhesion for holding the semiconductor dies. The redistribution layers are locally formed only where electrical connections are needed, while adhesion properties are maintained in regions where die support is required. This local differentiation resolves the conflict between electrical connectivity and adhesion stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration and testing of semiconductor dies by improving adhesion, facilitating debonding, and ensuring reliable electrical connectivity, thereby increasing yield and reducing costs in wafer-level packaging.
Implementation Method 1
epoxy-based thermal-release materials
Data Source
AI summary
A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.