Redistribution Package Structure for Wafer-Level Die Integration

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Solution Overview

Problem

Existing semiconductor device packaging technologies face challenges in efficiently integrating and connecting multiple semiconductor dies on a wafer level, particularly in ensuring reliable electrical connections and maintaining structural integrity during the packaging process.

Innovation Solution

A method involving the use of a debond layer on a carrier wafer, followed by the formation of a redistribution circuit structure with through vias and semiconductor dies, encapsulation, and subsequent build-up layers to create a stable and electrically connected package structure, utilizing materials like copper and dielectric polymers for enhanced adhesion and conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple semiconductor dies are integrated on a wafer level, then productivity and integration efficiency are improved, but structural integrity and reliability of electrical connections deteriorate due to delamination risks

Engineering Contradiction:

Improveintegration efficiencyVSAvoidstructural integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent segments the package structure into distinct functional layers: carrier wafer, debond layer, redistribution circuit structure, encapsulation layer, and build-up layers. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall structural integrity during wafer-level integration processes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The debond layer serves as an intermediary between the carrier wafer and the redistribution circuit structure. This intermediate layer prevents direct adhesion that could cause delamination during subsequent processing steps, while still enabling reliable electrical connections through the through vias and conductive structures

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If through vias and conductive structures are formed for electrical connections, then electrical connectivity is improved, but manufacturing complexity increases

Engineering Contradiction:

Improveelectrical connectionsVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Through vias are formed in the carrier wafer before the redistribution circuit structure is deposited. This preliminary action allows the conductive pathways to be established early in the manufacturing process, simplifying subsequent steps and ensuring reliable electrical connections are built into the structure from the foundation

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent employs composite material structures including metal layers (copper, aluminum), dielectric materials (polymers, oxides), and conductive pastes in combination. These composite materials provide both electrical conductivity and mechanical stability, achieving reliable electrical connections while managing manufacturing complexity through material property optimization

Inventive Principle:

Principle #40Composite materials

3Reliability

If encapsulation and build-up layers are added for protection, then reliability and structural stability are improved, but device complexity and manufacturing steps increase

Engineering Contradiction:

Improvestructural stabilityVSAvoidpackage structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The encapsulation layer is formed to encompass and protect the redistribution circuit structure, through vias, and conductive elements. Subsequent build-up layers are nested on top of the encapsulation, creating a protective hierarchy where each layer shields the structures beneath while adding functional capabilities

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The build-up layers modify physical and chemical parameters of the package structure, including surface topology, mechanical strength, and thermal properties. These parameter changes enhance structural stability and reliability without requiring fundamental redesign of the underlying architecture

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables reliable electrical connections and structural integrity of semiconductor packages, allowing for efficient integration of multiple dies while reducing delamination risks and enhancing the reliability of the circuitry.

Implementation Method 1

a debond layer on a carrier wafer

Methodology Applied

Scientific EffectAdhesion: Adhesive

Implementation Method 2

utilizing materials like copper and dielectric polymers for enhanced adhesion and conductivity

Methodology Applied

Scientific EffectElectrical Conduction: Conduction (electrical)

Data Source

PatentUS20250226317A1Package structure and method of manufacturing the same

Publication Date: 2025.07.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.