Redistribution Package Structure for High-Density Die Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating smaller electronic components into smaller packages while maintaining efficient connectivity and packaging density, as traditional packaging methods struggle to accommodate the reduced feature sizes and increased component density.
Innovation Solution
A package structure is formed using a carrier substrate with a release layer, where integrated circuit dies are adhered and connected via die connectors, encapsulated, and a front-side redistribution structure is created with multiple dielectric and metallization layers to facilitate efficient routing and connectivity, allowing for larger spacing between vias and metallization patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional packaging methods are used, then manufacturing simplicity is maintained, but packaging density and integration density cannot accommodate smaller feature sizes
Solution Approach 1:
The package structure is divided into multiple functional layers including dielectric layers, conductive layers, and semiconductor dies arranged in a stacked configuration. This segmentation allows each layer to perform specific functions while achieving high packaging density without overwhelming complexity in any single layer.
Solution Approach 2:
The patent transitions from traditional planar packaging to a three-dimensional stacked architecture. Multiple semiconductor dies and interconnect structures are arranged vertically across multiple layers, utilizing the third dimension to achieve higher integration density while maintaining manageable complexity through modular layer design.
2Manufacturing precision
If feature size is reduced to increase integration density, then more components fit in given area, but traditional packaging methods struggle to accommodate smaller components
Solution Approach 1:
Interconnect structures such as conductive vias and metallization patterns are formed in advance during semiconductor fabrication before die attachment. This preliminary formation of connection pathways simplifies subsequent packaging steps and enables handling of smaller feature sizes with existing manufacturing capabilities.
Solution Approach 2:
Dielectric layers serve as intermediary structures that electrically isolate and mechanically support conductive interconnects and semiconductor dies. These intermediary layers enable the integration of smaller features by providing structured pathways and isolation necessary for high-density packaging while maintaining manufacturing feasibility.
Data Source
AI summary
An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.