Redistribution Substrate Package Layout for Power Integrity

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Solution Overview

Problem

Semiconductor packages face issues such as system malfunctioning and performance degradation due to voltage noise generated in high-frequency bands, which affects power integrity (PI) properties.

Innovation Solution

The semiconductor package includes a base substrate, a redistribution substrate with insulating and redistribution pattern layers, a semiconductor chip, a chip structure, and an encapsulant. The semiconductor chip has a passive device mounted on its active surface, connected through a reduced connection path using wiring pattern layers, which improves power integrity without requiring an expensive silicon interposer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional semiconductor package structure is used, then the package can be manufactured with standard processes, but voltage noise is generated in high-frequency bands causing power integrity degradation

Engineering Contradiction:
Improvepower integrityVSAvoidvoltage noise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a silicon interposer as an intermediary substrate between the semiconductor chip and the organic substrate. The interposer contains ground pads that are electrically connected to ground through via holes, creating an intermediate ground reference that stabilizes the power signal and filters voltage noise in high-frequency bands, thereby improving power integrity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent transitions from a direct two-layer structure (chip on organic substrate) to a three-layer stacked structure (chip on silicon interposer on organic substrate). This dimensional addition allows the insertion of ground reference layers and via hole connections that provide noise filtering capability without significantly increasing the lateral footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a silicon interposer is used to improve power integrity, then voltage noise is removed effectively, but the manufacturing cost increases significantly

Engineering Contradiction:
Improvepower integrityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces the expensive silicon interposer with a cost-effective organic substrate that has been modified through standard PCB manufacturing processes. The organic substrate serves the same functional purpose of providing ground reference and noise filtering, but at a lower material and manufacturing cost, making it suitable for mass production

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If the connection path between chip and substrate is long, then the package structure is simple, but power integrity deteriorates due to voltage noise

Engineering Contradiction:
Improvepower integrityVSAvoidconnection path length
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The silicon interposer acts as an intermediary that provides multiple ground pads distributed across its surface, each connected to ground through via holes. This creates multiple short connection paths from the chip's power pads to ground references, replacing a single long connection path and thereby reducing inductance and voltage noise

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12205914B2Semiconductor package
Publication Date: 2025.01.21 SAMSUNG ELECTRONICS CO LTD
  • US12205914B2 patent drawing
  • US12205914B2 patent drawing
  • US12205914B2 patent drawing

AI summary

A semiconductor package includes a base substrate; a redistribution substrate disposed on the base substrate, and that includes first insulating layers and redistribution pattern layers disposed on the first insulating layers, respectively; a semiconductor chip disposed on the redistribution substrate and electrically connected to the redistribution pattern layers; and a chip structure disposed on the redistribution substrate adjacent to the semiconductor chip and electrically connected to the semiconductor chip through the redistribution pattern layers, wherein the semiconductor chip includes a body that has an active surface that faces the redistribution substrate; first and second contact pads spaced apart from each other below the active surface; a first bump structure and a passive device electrically connected to the first connection pad at a lower level from the first connection pad; and a second bump structure electrically connected to the second connection pad at a lower level from the second connection pad.