Redistribution Package Layout With Uneven TIM for Height Alignment
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in efficiently packaging semiconductor devices with asymmetrical heights, leading to inefficiencies in wafer-scale heterogenous integration and performance computing applications.
Innovation Solution
The implementation of asymmetrical semiconductor packages with varying thermal interface material (TIM) layers and redistribution structures to compensate for height differences, enhancing wafer-scale chip packaging density and computing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If asymmetrical semiconductor packages are packaged on a single wafer, then wafer-scale chip packaging density increases, but manufacturing complexity increases due to height differences
Solution Approach 1:
The patent applies asymmetry by intentionally designing semiconductor packages with different heights and configuring thermal interface material layers with varying thicknesses to match these height differences. This asymmetric configuration allows multiple packages with different functionalities and sizes to be integrated on a single wafer, thereby increasing packaging density while managing the complexity through systematic design rules.
Solution Approach 2:
The patent implements local quality by applying different thicknesses of thermal interface material layers to different packages based on their specific height requirements. Each package receives a customized TIM layer thickness (first thickness for first packages, second thickness for second packages), which compensates for height variations and enables planarization. This localized adaptation allows asymmetrical packages to coexist on the same wafer without compromising manufacturing feasibility.
2Productivity
If thermal interface material layers of different thicknesses are used to compensate height differences, then packaging density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the thickness parameter of thermal interface material layers to compensate for height differences between packages. By systematically varying the TIM layer thickness (first thickness vs. second thickness) based on package height requirements, the patent achieves height alignment and enables higher packaging density while maintaining controllable manufacturing precision through defined parameter relationships.
3Reliability
If asymmetrical packages are stabilized with different TIM layers, then computing performance enhances, but process complexity increases
Solution Approach 1:
The patent segments the thermal interface material application process into distinct steps for different package types. First packages receive a first TIM layer with a first thickness, while second packages receive a second TIM layer with a second thickness. This segmentation allows each package type to be optimized independently for its computing performance requirements while managing process complexity through systematic differentiation.
Data Source
AI summary
A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.