Redistribution Package Structure to Reduce Warping and Cracking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in reducing warping and cracking in package structures with multiple interconnects or integrated circuit dies, which can lead to joint failure and delamination.

Innovation Solution

The formation of multiple interconnect structures with conductive pillars and redistribution structures that improve planarity, reduce stress, and enhance electrical connectivity, thereby minimizing warping and cracking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple interconnect structures are used to improve electrical connectivity and reduce stress, then device reliability is improved, but warping and cracking increase

Engineering Contradiction:
Improvedevice reliabilityVSAvoidwarping and cracking
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The package structure is divided into multiple separate interconnect structures (first interconnect structure and second interconnect structure) that are laterally adjacent. Each interconnect structure independently provides electrical connectivity and stress distribution, preventing the warping and cracking that would occur with a single monolithic interconnect structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first and second interconnect structures are positioned within the same package structure, with each containing conductive pillars and redistribution structures. The underfill material is applied to both structures, creating a nested configuration where multiple functional elements coexist within a unified package architecture, improving reliability without excessive warping.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If multiple interconnect structures are used to enhance electrical connectivity, then device performance is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The first and second interconnect structures are manufactured using the same process steps: forming conductive pillars on core substrates, applying underfill material, and forming redistribution structures. By merging the manufacturing processes for both interconnect structures, the patent achieves enhanced electrical connectivity without proportionally increasing manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The underfill material is applied to both the first and second interconnect structures during the manufacturing process, before final assembly. This preliminary application of underfill material provides stress relief and planarity enhancement early in the manufacturing sequence, simplifying subsequent processing steps.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If multiple interconnect structures are used to reduce stress, then joint reliability is improved, but processing time increases

Engineering Contradiction:
Improvejoint reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The manufacturing process continues with both interconnect structures simultaneously present throughout the fabrication sequence. The underfill material is applied continuously to both structures, and redistribution structures are formed on both in an uninterrupted process flow, reducing total processing time compared to sequential manufacturing of separate structures.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20250087641A1Semiconductor Device and Method of Manufacture
Publication Date: 2025.03.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250087641A1 patent drawing
  • US20250087641A1 patent drawing
  • US20250087641A1 patent drawing

AI summary

A structure includes core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the redistribution structure.