Redistribution Structure Pad Layout for Chip Alignment Precision
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Solution Overview
Problem
The miniaturization of semiconductor packages requires precise alignment and efficient electrical connections between stacked semiconductor chips, which is challenging due to the miniaturization of pads and the need for high integration and compactness in electronic devices.
Innovation Solution
A semiconductor package design featuring a redistribution structure with a specific wiring pattern, pad pattern, and passivation layer that includes a connection terminal overlapping the extension part of the pad pattern, allowing for improved electrical connectivity and alignment between chips, including a seed pattern between the pad pattern and dielectric layer, and a connection terminal that exposes the extension part for efficient contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pads are miniaturized to achieve high integration of semiconductor devices, then integration density is improved, but alignment precision between stacked chips deteriorates
Solution Approach 1:
The pad structure is segmented into multiple functional parts: a connection part for electrical connection, an extension part for alignment reference, and a seed pattern for plating. This segmentation allows the alignment reference function to be separated from the electrical connection function, enabling precise alignment even with miniaturized pads.
Solution Approach 2:
The extension part of the pad pattern extends in a direction extending from the via part, creating a two-dimensional alignment reference structure. This dimensional extension provides a visible and measurable reference for alignment between stacked chips, solving the alignment precision problem while maintaining small pad footprints.
2Volume of moving object
If pads are miniaturized to achieve compact electronic products, then product size is reduced, but electrical connection reliability deteriorates
Solution Approach 1:
The seed pattern is formed in advance between the pad pattern and the via part, preparing the surface for subsequent plating processes. This preliminary action ensures reliable electrical connection by establishing a proper metallurgical bond before the conductive material is deposited, compensating for the reduced pad size.
Solution Approach 2:
Different regions of the pad structure have different functions optimized for their specific purposes: the connection part for electrical conductivity, the extension part for alignment, and the seed pattern for metallurgical bonding. This local optimization maintains connection reliability despite overall miniaturization.
3Quantity of substance
If complex wiring patterns are used to achieve high integration, then integration capability is improved, but fabrication complexity deteriorates
Solution Approach 1:
The pad pattern serves multiple functions simultaneously: electrical connection through the connection part, alignment reference through the extension part, and plating substrate through the seed pattern. This multi-functionality reduces the need for separate structures, simplifying fabrication while maintaining high integration capability.
Data Source
AI summary
A semiconductor package includes: a first wiring pattern; a dielectric layer that covers the first wiring pattern; a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern; a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a first surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern; and a seed pattern between the extension part and the dielectric layer.