Redistribution Connection Trees for Dense Semiconductor Power Delivery
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in efficiently connecting semiconductor dies to packages, leading to issues with thermal and connection density, signal integrity, and excess metal density, which hinder advancements in semiconductor performance and reliability.
Innovation Solution
The implementation of redistribution structures with concentric hexagonal connection trees, utilizing via structures and conductive planes, minimizes lateral distance between vias and reduces excess metal density, thereby enhancing connectivity and reducing impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional connection structures are used to connect semiconductor dies to packages, then connections can be established, but thermal and connection density increase excessively leading to heat management issues and signal integrity problems
Solution Approach 1:
The connection structure is segmented into multiple functional layers including die attach layer, redistribution layer, and package substrate layer, each performing specific functions. This segmentation allows optimization of metal density in each layer independently, reducing overall excess metal while maintaining signal integrity through specialized design of each segment.
Solution Approach 2:
The patent applies local quality by varying metal density and trace width based on local requirements - higher metal density in power delivery regions, optimized trace geometry in signal regions, and selective via placement. This localized optimization reduces unnecessary metal throughout the structure while maintaining signal integrity where required.
2Reliability
If more via structures are added to maximize connections between layers, then connectivity improves, but manufacturing complexity and lateral distance constraints become more difficult to manage
Solution Approach 1:
The via structures are organized in nested patterns where vias in upper layers are positioned within or adjacent to vias in lower layers, creating a hierarchical nesting arrangement. This nesting maximizes connectivity between layers while maintaining regular, manageable patterns that simplify manufacturing processes and reduce lateral distance constraints.
Solution Approach 2:
The patent transitions from two-dimensional via placement to three-dimensional via nesting across multiple layers, utilizing the vertical dimension to maximize connectivity. By stacking vias vertically and organizing them in nested patterns across layers, the design achieves high connectivity without increasing lateral complexity, as the additional connectivity is achieved through the vertical dimension.
3Reliability
If metal content is increased to reduce impedance and improve signal delivery, then signal integrity improves, but excess metal density creates manufacturing challenges and increased device size
Solution Approach 1:
The patent applies local quality by varying metal content based on local signal requirements - higher metal content and wider traces in regions requiring low impedance for power delivery, optimized metal content for signal integrity in critical signal paths, and reduced metal content in non-critical regions. This localized optimization reduces overall metal content while maintaining signal delivery performance where required.
Solution Approach 2:
The patent utilizes parameter changes by varying trace width, via diameter, and metal thickness as design parameters to optimize the balance between impedance control and metal content. By adjusting these geometric parameters locally throughout the structure, the design achieves adequate signal delivery with minimized overall metal content, avoiding the need for uniformly high metal density throughout the entire device.
Data Source
AI summary
A semiconductor device includes a first connector, a second connector, and a redistribution structure disposed between the first connector and the second connector. The redistribution structure includes a first connection tree electrically connecting the first connector to the second connector. The first connection tree includes a plurality of first conductive pads disposed in a plurality of respective levels, and a plurality of first via structures each disposed between adjacent ones of the plurality of first conductive pads. Any lateral end of each of the plurality of first conductive pads is spaced from the first connector within a first minimum pitch associated with the second connector.