Redistribution Structure for Shorter Signal Paths in Stacked Chips

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Solution Overview

Problem

The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in data signal transmission and power consumption.

Innovation Solution

A semiconductor device design featuring a plug structure and redistribution layers that allow data signal transmission through upper and lower bonding pads and redistribution layers without passing through conductive features, reducing transmission distance and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If data signal transmission path is extended through conductive features and functional units, then signal transmission distance increases, but power consumption increases and performance deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidsignal transmission distance
Core Design Contradiction:
Use of energy by moving objectVSLength of moving object

Solution Approach 1:

The patent segments the signal transmission path into separate functional layers: data signals are transmitted through dedicated redistribution layers while control signals pass through plug structures and functional units. This segmentation allows data signals to bypass unnecessary conductive features and functional units, reducing transmission distance and power consumption while maintaining proper signal routing.

Inventive Principle:
Principle #1Segmentation

2Productivity

If semiconductor device dimensions are scaled down, then computing ability demand is met, but quality, yield, performance, and reliability issues increase

Engineering Contradiction:
Improvecomputing abilityVSAvoiddevice quality and yield
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from planar signal routing to a three-dimensional stacked architecture with multiple chips bonded together. Data signals are transmitted through redistribution layers in the horizontal plane while control signals travel vertically through plug structures. This dimensional change allows continued scaling of computing density without proportionally increasing signal transmission distances, thereby maintaining reliability and yield.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If signal transmission path includes multiple conductive features and functional units, then device functionality is achieved, but device complexity increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidsignal transmission path complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts the data signal transmission function from the control signal path by creating dedicated redistribution layers for data signals. This separation removes unnecessary conductive features and functional units from the data signal path, reducing complexity while preserving all required device functionalities through the differentiated signal routing paths.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11764178B2Semiconductor device with redistribution structure and method for fabricating the same
Publication Date: 2023.09.19 NAN YA TECH
  • US11764178B2 patent drawing
  • US11764178B2 patent drawing
  • US11764178B2 patent drawing

AI summary

A semiconductor device includes a first chip including a first substrate including a center region and a peripheral region; a first center bonding pad above the center region of the first substrate; and a first peripheral bonding pad above the peripheral region of the first substrate; and a second chip on the first chip and including: a plurality of peripheral upper bonding pads at a peripheral region of the second chip and respectively on the first center bonding pad and the first peripheral bonding pad; a plurality of redistribution structures respectively on the plurality of peripheral upper bonding pads and extending toward a center region of the second chip; a plurality of center lower bonding pads at the center region of the second chip and respectively on the plurality of redistribution structures; and a plurality of storage units electrically coupled to the plurality of center lower bonding pads.