Redistribution Structure for 3D Package Routing Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in bonding integrated circuit chips directly onto substrates due to limitations in two-dimensional integration, which hinders the development of three-dimensional package structures that can accommodate high-density components for high-speed transmission and computing applications.
Innovation Solution
The formation of a chip-on-wafer-on-substrate package using an interposer with a redistribution structure, where conductive vias are formed with a higher aspect ratio and a thicker polyimide layer to enhance routing density, reliability, and prevent resistive-capacitive delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional integration is used to increase component density, then more components can be integrated into a given area, but the ability to bond integrated circuit chips directly onto substrates is surpassed and three-dimensional package structures are required
Solution Approach 1:
The patent transitions from two-dimensional integration to three-dimensional package structures by introducing vertical stacking of chips and interposers. This allows continued increase in component density by utilizing the third dimension (height/depth) rather than being constrained to the planar surface area, thereby resolving the contradiction between density and bonding limitations.
2Quantity of substance
If conductive vias with smaller width and larger height are formed, then routing density is increased for high-speed transmission, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the dimensional parameters of conductive vias by forming them with smaller widths and larger heights (higher aspect ratios). This parameter optimization increases routing density within the available space while the patent addresses the associated manufacturing precision challenges through specific formation processes and structural designs.
3Reliability
If a thicker polyimide layer is formed, then reliability is increased and resistive-capacitive delay is prevented, but device complexity increases
Solution Approach 1:
The patent increases the thickness parameter of the polyimide layer to enhance reliability and prevent resistive-capacitive delay in high-speed transmission. This parameter change improves signal integrity and electrical performance, with the associated complexity managed through integrated process design.
Data Source
AI summary
A method includes forming a redistribution structure, wherein forming the redistribution structure includes forming a first conductive material on a portion of a first seed layer, forming a mask over the first seed layer and the first conductive material, wherein an opening in the mask at least partially exposes the first conductive material, forming a first conductive via in the opening, etching portions of the first seed layer using the first conductive material as an etching mask, depositing a first insulating layer over the first conductive via, the first conductive material and remaining portions of the first seed layer, and etching the first insulating layer such that a portion of the first conductive via protrudes above a top surface of the first insulating layer, and attaching a first die to the redistribution structure using first electrical connectors.