Redistribution Structure Layout for CTE Stress Buffering
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Solution Overview
Problem
The semiconductor industry faces challenges in managing stress caused by coefficient of thermal expansion (CTE) mismatch in semiconductor packages, leading to bending and deformation of metallization patterns, which can result in reliability issues.
Innovation Solution
The use of flexibly-shaped metallization patterns with 'C'-like or 'U'-like shapes surrounded by conforming dielectric layers, along with UBM structures featuring via, pad, and column portions with specific arrangements to reduce stress, including wider pad portions and laterally shifted centers, enhances the reliability of redistribution structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If rigid metallization patterns are used in semiconductor packages, then manufacturing precision is improved, but stress from CTE mismatch causes bending and deformation leading to reliability issues
Solution Approach 1:
The patent applies flexible dielectric layers surrounding the metallization patterns, allowing the structure to bend and deform elastically in response to thermal expansion stress without breaking. This flexible encapsulation buffers the stress from CTE mismatch while maintaining the integrity of the metallization patterns, resolving the contradiction between manufacturing precision and reliability.
2Ease of manufacture
If standard straight metallization patterns are used, then ease of manufacture is improved, but stress concentration occurs leading to structural failure
Solution Approach 1:
The patent introduces curved or bent metallization patterns instead of straight lines. These curved patterns reduce stress concentration by distributing thermal expansion forces more evenly along the conductive paths, preventing structural failure while remaining compatible with standard photolithography manufacturing processes.
3Area of stationary object
If tightly packed metallization patterns are used, then area utilization is improved, but stress from thermal expansion causes deformation and reliability issues
Solution Approach 1:
The flexible dielectric encapsulation allows tightly packed metallization patterns to accommodate thermal expansion stress through elastic deformation, enabling high area utilization while maintaining reliability. The flexible layers act as stress buffers that prevent cracking even when patterns are closely spaced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively buffers stress in semiconductor packages, increasing the reliability of redistribution structures by allowing them to bend and deform without breaking, thereby improving the overall package structure's integrity.
Implementation Method 1
flexibly-shaped metallization patterns with 'C'-like or 'U'-like shapes surrounded by conforming dielectric layers, along with UBM structures featuring via, pad, and column portions with specific arrangements to reduce stress, including wider pad portions and laterally shifted centers, enhances the reliability of redistribution structures
Data Source
AI summary
A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.