Redistribution Structure With Offset Vias for Fine-Pitch IC Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller and more densely packed semiconductor devices due to limitations in packaging techniques, particularly in forming redistribution structures over integrated circuit dies with reduced size and pitch, which affects the integration density and component density in Package-on-Package (PoP) technology.
Innovation Solution
The formation of redistribution structures with laterally shifted vias over integrated circuit dies, where vias partially land on connectors, allowing for reduced size and pitch, and enabling enlarged die shift/rotation windows, is achieved through specific processing steps involving insulating layers and metallization patterns, allowing for efficient packaging of integrated circuit dies with varying densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but integration density and component density cannot be sufficiently increased
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging (Package-on-Package), utilizing the vertical dimension to increase component density. Multiple semiconductor packages are stacked vertically with redistribution structures enabling inter-package connections, thereby achieving higher integration density without proportionally increasing footprint area.
Solution Approach 2:
The patent implements nested packaging where smaller packages are positioned within or between larger packages in a hierarchical arrangement. The redistribution structures are nested within the package layers, with vias penetrating through multiple levels to establish connections between stacked packages, creating a compact nested configuration that maximizes space utilization.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the inter-package connection structure into discrete segments: separate redistribution layers, distinct via structures, and modular package units. This segmentation allows each component to be optimized and manufactured independently with standard precision, avoiding the need for ultra-precise monolithic feature sizes while achieving high overall integration density through the assembled segmented structure.
3Area of stationary object
If smaller package sizes are used, then device footprint is reduced, but connectivity and signal distribution become more difficult
Solution Approach 1:
The patent resolves connectivity challenges in small packages by moving connections from the two-dimensional plane to the third dimension. Redistribution structures are formed in multiple stacked layers with vias providing vertical interconnections between layers, enabling complex signal routing and distribution within a compact footprint by utilizing the vertical stacking dimension for signal paths.
Data Source
AI summary
A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.