Redistribution Structure Layout for Lower Parasitic Capacitance

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Solution Overview

Problem

The increasing demand for miniaturized and highly integrated semiconductor packages is hindered by parasitic capacitance in wiring, which affects electrical reliability.

Innovation Solution

A redistribution structure with a via layer and wiring layer configuration, featuring a metal plate and insulation patterns that penetrate the metal plate, with exposed outer side surfaces of the insulation patterns coplanar with the metal plate, reducing parasitic capacitance and improving electrical reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wiring is miniaturized and highly integrated to meet demand for smaller semiconductor packages, then functionalization and integration are improved, but parasitic capacitance increases and electrical reliability deteriorates

Engineering Contradiction:

Improvefunctionalization and integrationVSAvoidelectrical reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The wiring structure is segmented into multiple layers (first wiring layer, second wiring layer) with insulation patterns positioned between them. This segmentation allows for better control of parasitic capacitance by separating conductive elements and managing their spatial relationships, thus maintaining electrical reliability while enabling miniaturization and high integration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Insulation patterns are strategically positioned at specific locations where parasitic capacitance is most problematic - between wiring layers and at side surfaces of metal plates. This localized application of insulation material optimizes the reduction of parasitic capacitance without requiring complete insulation throughout the entire structure, enabling miniaturization while maintaining electrical performance.

Inventive Principle:

Principle #3Local quality

2Volume of moving object

If wiring is miniaturized to reduce package size, then package dimensions are reduced, but parasitic capacitance in wiring increases

Engineering Contradiction:

Improvepackage sizeVSAvoidparasitic capacitance

Core Design Contradiction:

Volume of moving objectVSObject-generated harmful factors

Solution Approach 1:

The solution moves from two-dimensional planar wiring to three-dimensional stacked wiring layers. By utilizing the vertical dimension with multiple wiring layers separated by insulation patterns, the design achieves higher integration density (reducing package size) while controlling parasitic capacitance through vertical separation of conductive elements.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Insulation patterns act as intermediary elements positioned between adjacent wiring layers and at critical interfaces. These insulation patterns mediate the electromagnetic interaction between conductive elements, reducing parasitic capacitance while allowing the wiring structure to be miniaturized and highly integrated.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20260018504A1Redistribution structure and semiconductor package including the same

Publication Date: 2026.01.15 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a redistribution structure having reduced parasitic capacitance. The redistribution structure may include a via layer and a wiring layer disposed on the via layer in a first direction perpendicular to the via layer, the wiring layer including a metal plate and a first insulation pattern configured to penetrate the metal plate in the first direction. An outer side surface of the first insulation pattern may be exposed from a side surface of the metal plate.