Semiconductor package and method comprising formation of redistribution structure and interconnecting die

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in achieving high integration density and reliable electrical connections between stacked semiconductor packages due to warpage mismatch and coefficient of thermal expansion (CTE) issues, which are exacerbated by the use of interposers and solder connections.

Innovation Solution

A solder-free connection is established through embedded local interconnect components within a redistribution structure, which provides electrical routing and connection between integrated circuit dies, reducing the need for interposers and minimizing CTE mismatch, while maintaining low contact resistance and high reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder connections are used to connect integrated circuit dies to redistribution structure, then electrical connection is established, but electromigration issues and reliability problems occur

Engineering Contradiction:

Improveconnection reliabilityVSAvoidelectromigration issues

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent removes solder connections from the system by implementing direct copper-to-copper bonding between the interconnect component and the redistribution structure. This extraction of the harmful solder material eliminates electromigration issues while maintaining electrical connectivity through the direct metal-to-metal bond.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the solder-based mechanical-chemical bonding system with a direct copper bonding system. This substitution eliminates the harmful effects of solder (electromigration, thermal expansion mismatch) while achieving reliable electrical connection through direct copper-to-copper contact, potentially using techniques like electroplating or direct bonding.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If interposers are used to provide electrical routing between dies, then connectivity is achieved, but CTE mismatch and warpage issues are exacerbated

Engineering Contradiction:

Improveelectrical routing capabilityVSAvoidCTE mismatch

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent removes the interposer layer from the package structure by integrating the electrical routing function directly into the redistribution structure formed on the substrate. This elimination of the interposer removes the source of CTE mismatch and warpage problems while maintaining the necessary electrical connectivity through the substrate-based redistribution network.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent combines the electrical routing function (previously performed by the interposer) with the substrate-based redistribution structure. By merging these functions into a single integrated system, the patent eliminates the interface between dissimilar materials that causes CTE mismatch, while achieving the same electrical connectivity goal.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If traditional packaging techniques are used, then manufacturing simplicity is maintained, but integration density and component density are limited

Engineering Contradiction:

Improveintegration densityVSAvoidpackaging structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent transitions from traditional planar packaging to a three-dimensional stacked architecture where multiple integrated circuit dies are vertically positioned over the substrate. This dimensional change enables higher integration density by utilizing the vertical space above the substrate, allowing multiple functional layers to be stacked without significantly increasing the footprint area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where the first and second integrated circuit dies are positioned and connected through the redistribution structure in a stacked configuration. This nesting approach allows multiple functional components to be integrated within a compact vertical arrangement, achieving high component density while maintaining manufacturing feasibility through sequential assembly steps.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS20250308997A1Semiconductor package and method comprising formation of redistribution structure and interconnecting die

Publication Date: 2025.10.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

In an embodiment, a structure includes a core substrate, a redistribution structure coupled to a first side of the core substrate, the redistribution structure including a plurality of redistribution layers, each of the plurality of redistribution layers comprising a dielectric layer and a metallization layer, and a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure on the substrate, and bond pads on the interconnect structure, the bond pads of the first local interconnect component physically contacting a metallization layer of a second redistribution layer, the second redistribution layer being adjacent the first redistribution layer, the metallization layer of the second redistribution layer comprising first conductive vias, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component.