Redistribution Structure Layout to Reduce Fan-Out Package Warpage
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Solution Overview
Problem
Conventional semiconductor packaging techniques face challenges with high warpage issues, leading to cracking of bumps and adverse effects on yield due to the conventional flow of picking and placing package components on fan-out structures before laser drilling and cleaning processes.
Innovation Solution
A method involving the formation of a redistribution structure over a temporary carrier with conductive patterns and vias, followed by de-bonding and placement on a tape frame, where conductive terminals are formed and subsequently attached to a circuit substrate, omitting the need for laser drilling and ball placement to reduce warpage and simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If package components are picked and placed on fan-out structure before laser drill and clean process, then the packaging process can be completed, but the bump is easy to crack due to high warpage issue and the yield is adversely affected
Solution Approach 1:
The patent applies preliminary action by performing laser drilling and cleaning processes on the fan-out structure before picking and placing package components. This sequence reversal prevents warpage-induced bump cracking by establishing a stable base structure first, then adding components, thereby eliminating the reliability issue while maintaining productivity
2Ease of manufacture
If conventional pick and place process is used before laser drill, then manufacturing steps can be completed, but the process complexity increases and yield decreases
Solution Approach 1:
The patent inverts the conventional manufacturing sequence by performing laser drilling and cleaning before component placement instead of after. This inversion simplifies the overall process by eliminating warpage-related rework and yield losses, making the manufacturing easier despite the apparent addition of process steps
Data Source
AI summary
A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.