Redistribution Substrate Capacitor Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for forming capacitors in redistribution layers for semiconductor packages are complex, leading to increased package size and deterioration in operating characteristics, and fail to efficiently integrate high-capacity connections due to the scaling down of semiconductor chips.
Innovation Solution
A redistribution substrate is designed with a capacitor integrated between conductive patterns, utilizing a barrier layer, dielectric layer, and top electrode stacked on the conductive pattern, allowing for compact packaging and preventing dielectric layer damage from metal diffusion, thereby enhancing reliability and compactness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors are formed using existing methods in redistribution layers, then capacitor functionality is achieved, but the manufacturing process becomes complex and package size increases
Solution Approach 1:
The patent merges the capacitor formation process with the existing redistribution layer manufacturing process. The capacitor structure is integrated into the redistribution layer stack, sharing common layers (conductive patterns, dielectric layers, barrier layers) and manufacturing steps (depositing, patterning, etching). This consolidation eliminates the need for separate capacitor fabrication processes, reducing overall manufacturing complexity while maintaining capacitor functionality.
2Reliability
If existing capacitor formation methods are used, then capacitor functionality is achieved, but package size increases
Solution Approach 1:
The capacitor structure is nested within the redistribution layer architecture. The capacitor's conductive patterns, dielectric layers, and barrier layers are embedded within the existing redistribution layer stack, utilizing the same vertical space and horizontal footprint. This nesting approach allows the capacitor to share the package area with other redistribution layer components, eliminating the need for additional dedicated capacitor space and reducing overall package size.
3Productivity
If semiconductor chips are scaled down to increase integration, then high integration is achieved, but efficient integration of high-capacity connections becomes difficult
Solution Approach 1:
The patent transitions from two-dimensional planar capacitor structures to three-dimensional vertical structures within the redistribution layers. By stacking multiple conductive patterns and dielectric layers vertically, the capacitor achieves higher capacitance density in the vertical dimension. This dimensional transition allows high-capacity connections to be integrated efficiently even as chip area decreases, maintaining connection capacity while increasing integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of capacitors within the redistribution substrate reduces package size and improves reliability by eliminating the need for additional space and preventing dielectric layer damage, while maintaining high-capacity connections.
Implementation Method 1
preventing dielectric layer damage from metal diffusion
Implementation Method 2
a capacitor between the first conductive pattern and the first via
Data Source
AI summary
A redistribution substrate includes a first conductive pattern including a first lower pad and a second lower pad, the first and second lower pads being within a first insulating layer, a second conductive pattern including a first upper pad and a second upper pad, the first and second upper pads being on the first insulating layer, a first via connecting the first lower pad and the first upper pad to each other in the first insulating layer, a second via connecting the second lower pad and the second upper pad to each other in the first insulating layer, and a capacitor between the first lower pad and the first via.