Redistribution Substrate Layout for Compact Semiconductor Packaging
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Solution Overview
Problem
Current semiconductor packages face challenges in reducing size while maintaining reliability and electrical connectivity, particularly in the formation of redistribution substrates without the use of printed circuit boards.
Innovation Solution
A method for fabricating a semiconductor package that involves forming a redistribution substrate with multiple insulating layers and seed layers, where redistribution patterns are created through electroplating and planarization processes to achieve precise electrical connections and compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a redistribution substrate is formed without a PCB to reduce package size, then the package size is reduced, but the manufacturing complexity increases
Solution Approach 1:
The redistribution substrate is divided into multiple insulating layers (first insulating layer, second insulating layer) with redistribution patterns formed at different levels. This segmentation allows complex electrical connections to be achieved through multiple simpler layers rather than a single complex structure, resolving the contradiction between reduced package size and manufacturing complexity.
Solution Approach 2:
The patent transitions from a planar PCB structure to a three-dimensional stacked configuration with multiple insulating layers and vertically arranged redistribution patterns. This dimensional change enables compact packaging while distributing the complexity across multiple layers, making the manufacturing process more manageable despite the increased vertical complexity.
2Reliability
If multiple insulating layers and redistribution patterns are formed to improve electrical connectivity, then electrical characteristics are improved, but the number of fabrication steps increases
Solution Approach 1:
The patent combines the formation of redistribution patterns with the formation of insulating layers in an integrated multi-step process. The seed layer is formed to define the redistribution pattern location, followed by electroplating to create the conductive pattern, and then insulating layers are formed to cover and isolate the patterns. This merging of multiple functions into a coordinated process sequence improves electrical connectivity while managing fabrication complexity through systematic integration.
3Manufacturing precision
If planarization process is performed to expose redistribution patterns for precise connections, then manufacturing precision is improved, but the process time increases
Solution Approach 1:
The planarization process is performed in advance to expose the redistribution patterns before subsequent fabrication steps. By pre-planarizing the surface to expose the patterns, the patent ensures precise alignment and connection points are established beforehand, improving manufacturing precision while allowing subsequent steps to proceed more efficiently without re-work.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the creation of smaller semiconductor packages with improved electrical characteristics and reliability by ensuring uniformity and precision in the formation of redistribution patterns, facilitating efficient electrical connections between semiconductor chips and the substrate.
Implementation Method 1
forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer
Implementation Method 2
a seed layer disposed between the first insulating layer and the redistribution pattern
Data Source
AI summary
A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.