Redistribution Substrate CTE Matching for Semiconductor Warpage
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Solution Overview
Problem
Semiconductor packages face warpage issues due to mismatched coefficients of thermal expansion (CTE) between the conductive pattern and the semiconductor chip, which complicates achieving compact size and high performance in densely integrated electronic devices.
Innovation Solution
A semiconductor package design incorporating a redistribution substrate with a metal layer having a high modulus and CTE matching the conductive pattern, surrounded by a mold layer, which balances the CTE mismatch and enhances thermal conductivity to prevent warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are densely mounted on printed circuit boards to achieve greater integration, then integration density is improved, but warpage occurs due to CTE mismatch
Solution Approach 1:
The patent introduces a redistribution substrate as an intermediary layer between the semiconductor chip and the printed circuit board. This substrate has a coefficient of thermal expansion (CTE) that matches the semiconductor chip, serving as a mediator that eliminates the CTE mismatch problem. The redistribution substrate transfers thermal expansion forces uniformly, preventing warpage while enabling dense chip mounting.
Solution Approach 2:
The patent changes the CTE parameter of the substrate layer by using a redistribution substrate with specifically matched CTE properties. By selecting materials and designing the substrate structure to have a CTE that matches the semiconductor chip, the thermal expansion characteristics are optimized to prevent warpage during temperature cycling and operation.
2Volume of moving object
If compact size is pursued to meet high performance requirements, then device size is reduced, but warpage control becomes more difficult
Solution Approach 1:
The redistribution substrate acts as a mediator that decouples the size reduction from warpage control. By placing this intermediate layer with matched CTE between the chip and the larger PCB, the patent enables compact packaging while the substrate absorbs and distributes thermal stresses, preventing warpage even in small-form-factor devices.
3Reliability
If bonding wires or bumps are used to connect semiconductor chips to PCB, then electrical connection is achieved, but CTE mismatch causes warpage
Solution Approach 1:
The redistribution substrate serves as an intermediary connection layer between the semiconductor chip and the PCB. Instead of directly connecting chips to PCB with bonding wires or bumps through a CTE-mismatched substrate, this intermediate layer with matched CTE properties is introduced. It provides reliable electrical connection pathways while eliminating the warpage-causing CTE mismatch at the critical chip-substrate interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents warpage by matching CTE and improving thermal conductivity, allowing for compact and high-performance semiconductor packages.
Implementation Method 1
metal layer having a high modulus and CTE matching the conductive pattern
Implementation Method 2
mold layer, which balances the CTE mismatch and enhances thermal conductivity to prevent warpage
Implementation Method 3
mold layer, which balances the CTE mismatch and enhances thermal conductivity to prevent warpage
Data Source
AI summary
A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.