Redistribution Substrate Package Layout for Shorter Electrical Paths
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving reduced size and increased reliability, particularly in the integration of passive devices and semiconductor chips.
Innovation Solution
A semiconductor package design incorporating a redistribution substrate with a dielectric layer, conductive patterns, and passive devices such as capacitors, which includes a specific configuration of seed and metal patterns to enhance electrical connectivity and reduce package size while maintaining reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive devices are embedded in through holes of a core substrate, then electrical connectivity is achieved, but the package size and electrical path length are increased
Solution Approach 1:
The patent transitions from planar embedding of passive devices in through-holes to vertical stacking architecture where passive devices are positioned above the core substrate in multiple layers, utilizing the height dimension to reduce the horizontal footprint and overall package size while maintaining electrical connectivity through vertical vias
Solution Approach 2:
The patent implements nested stacking where active devices are placed above passive devices in a vertical arrangement, with each layer containing components that are vertically aligned and electrically connected through vias, creating a compact three-dimensional integrated structure
2Ease of manufacture
If passive devices are mounted on the surface of the core substrate, then integration is simplified, but the electrical path between passive devices and semiconductor chips is increased
Solution Approach 1:
The patent moves passive devices from the horizontal plane to the vertical dimension by stacking them above the core substrate, enabling direct vertical electrical connections through vias that significantly shorten the electrical path length compared to horizontal routing on the substrate surface
3Volume of moving object
If multiple layers of conductive patterns and dielectric layers are added to reduce package size, then package density increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the package into distinct modular layers including core substrate, passive device layer, active device layer, and interconnect layers, with each layer serving a specific function and being manufacturable through standardized processes, thereby managing complexity through systematic segmentation
Solution Approach 2:
The patent employs universal conductive patterns and dielectric layer structures that serve multiple functions including electrical interconnection, mechanical support, and signal routing across different device layers, reducing the need for specialized components and simplifying the overall manufacturing process
Data Source
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AI summary
Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal.