Redistribution Substrate Layout for Reliable Semiconductor Interconnects
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Solution Overview
Problem
Existing semiconductor packages face challenges in reliability and compactness due to the complexity of interconnects and the need for multiple conductive patterns, which can lead to electrical interference and poor connections.
Innovation Solution
A semiconductor package is designed with a redistribution substrate that includes under-bump patterns with a first part and a wider second part, which serves as a routing line, and a method of fabrication that involves electroplating and selective etching to form conductive patterns without undulations, enhancing electrical connections and package reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple conductive patterns are used to increase reliability, then electrical connections are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines multiple conductive patterns (signal and ground) into a single integrated under-bump pattern structure. The under-bump pattern includes both signal conductive regions and ground conductive regions formed as one unified element, eliminating the need for separate fabrication processes for each pattern type and reducing overall device complexity while maintaining electrical connection reliability
Solution Approach 2:
The under-bump pattern serves multiple functions simultaneously: it provides electrical connection for signals, establishes ground references, and enables redistribution of interconnects. This multi-functional design reduces the number of separate components needed and simplifies the overall package structure while improving reliability
2Ease of manufacture
If conventional electroplating is used to form under-bump patterns, then conductive patterns are created, but undulations occur on the pattern surfaces
Solution Approach 1:
The patent applies a planarization layer over the electroplated under-bump patterns before proceeding with subsequent fabrication steps. This preliminary planarization action removes surface undulations created during electroplating, ensuring a flat surface for accurate alignment and formation of subsequent conductive patterns and dielectric layers
Solution Approach 2:
The patent introduces a planarization layer as an intermediary element between the electroplated under-bump patterns and the subsequent fabrication processes. This intermediate layer absorbs the surface irregularities from electroplating and provides a uniform base for subsequent pattern formation, eliminating the harmful effect of undulations without requiring rework of the electroplating process itself
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution increases the reliability and compactness of semiconductor packages by reducing undulations in conductive patterns, improving electrical connections, and preventing electrical interference, while simplifying the fabrication process.
Implementation Method 1
forming under-bump patterns in the first openings and the first guide openings and that cover the under-bump seed layer, by performing an electroplating process in which the under-bump seed layer is used as an electrode
Data Source
AI summary
A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.