Redistribution Substrate Recess Structure for Pad Via Reliability
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Solution Overview
Problem
Existing semiconductor packages face reliability issues and electrical failures due to reduced contact areas between pad vias and redistribution patterns, leading to potential cracks and disconnections under thermal stress.
Innovation Solution
The semiconductor package incorporates a dimple structure in the top surface of the second interconnection, increasing the contact area between the pad via and the redistribution pattern, and selectively forming this structure in high-risk areas to prevent cracks and electrical failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the contact area between pad via and redistribution pattern is reduced to enable miniaturization, then the semiconductor package size is reduced, but the reliability deteriorates due to potential cracks and disconnections under thermal stress
Solution Approach 1:
The patent applies curvature by forming a recess region (dimple) in the top surface of the second interconnection. This curved/concave structure increases the contact area between the pad via and the redistribution pattern by allowing the pad via to nestle into the recess, thereby improving mechanical bonding and thermal stress resistance without increasing the overall package footprint.
Solution Approach 2:
The recess region is selectively formed only in specific high-risk areas where pad vias are located, rather than uniformly across the entire redistribution substrate. This localized modification approach enhances reliability at critical connection points while maintaining the miniaturized overall package design.
2Reliability
If the contact area between pad via and redistribution pattern is increased to improve reliability, then the resistance to thermal stress is improved, but the device complexity increases due to additional structural features
Solution Approach 1:
The recess region is formed only in specific locations where pad vias are positioned, rather than across the entire redistribution substrate. This selective local modification improves reliability at critical interfaces while keeping the overall structural complexity low and maintaining compatibility with existing manufacturing processes.
3Reliability
If the recess region is formed in the second interconnection to increase contact area, then the electrical characteristics are improved by reducing disconnections, but the manufacturing precision requirements increase
Solution Approach 1:
The recess region is formed in advance during the redistribution substrate fabrication process, before the pad vias are attached. This preliminary preparation of the contact surface allows for better control of the recess geometry and ensures that the pad via will properly engage with the recessed area, reducing variability in the final connection quality.
Data Source
AI summary
A semiconductor package includes a redistribution substrate having a semiconductor chip mounted on a top surface thereof with and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate includes a first redistribution pattern on a bottom surface of the connection terminal and comprising a first via and a first interconnection on the first via, a pad pattern between the first redistribution pattern and the connection terminal and comprising a pad via and a pad on the pad via, and a second redistribution pattern between the first redistribution pattern and the pad pattern and comprising a second via and a second interconnection on the second via with a recess region where a portion of a top surface of the second interconnection is recessed. A bottom surface of the recess region is located at a lower level than a topmost surface of the second interconnection.