Redistribution Substrate Layout for Shorter Chip Signal Paths
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Solution Overview
Problem
Existing semiconductor packages face challenges in miniaturization, weight reduction, and cost reduction while maintaining effective signal transmission and integration capabilities.
Innovation Solution
A semiconductor package design incorporating a package substrate with multiple redistribution layers and connection substrates, featuring connection holes and specific chip configurations to reduce connection lengths and enhance signal transmission speed and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple redistribution layers and connection substrates are used to reduce connection lengths and improve signal transmission, then signal transmission speed and stability are improved, but device complexity increases
Solution Approach 1:
The package structure is divided into multiple redistribution layers (first and second redistribution layers) and connection substrates with connection holes, creating segmented connection paths that reduce overall connection length and improve signal transmission by breaking down the single complex path into manageable segments
Solution Approach 2:
The patent utilizes vertical stacking of multiple redistribution layers and connection substrates, transitioning from a planar two-dimensional layout to a three-dimensional vertical architecture, thereby reducing connection lengths and improving signal transmission without increasing the package footprint
2Productivity
If chips are densely integrated to increase integration density, then productivity and performance are improved, but manufacturing precision requirements increase
Solution Approach 1:
Redistribution layers serve as intermediary structures between chips and external connections, providing additional connection points and routing paths that accommodate higher integration density while maintaining manufacturable precision levels through standardized pitch and layout patterns
Solution Approach 2:
The patent replaces traditional mechanical wire bonding with direct chip-to-substrate mounting using bumps or pads, eliminating the need for complex wire manipulation equipment and reducing manufacturing precision requirements while enabling higher integration density
3Speed
If connection lengths are reduced to improve signal transmission, then signal speed is improved, but device complexity increases
Solution Approach 1:
Connection substrates with connection holes are nested within the package structure, with first and second connection chips mounted on opposite sides of the same substrate, creating a compact nested arrangement that minimizes connection lengths while avoiding excessive structural complexity through standardized hole patterns
Data Source
AI summary
A semiconductor package includes: a package substrate; a first re-distribution layer disposed on the package substrate; a second re-distribution layer disposed between the package substrate and the first re-distribution layer; a connection substrate interposed between the first re-distribution layer and the second re-distribution layer, wherein a connection hole penetrates the connection substrate; a first semiconductor chip mounted on a first surface of the first re-distribution layer; a first connection chip mounted on a second surface, opposite to the first surface, of the first re-distribution layer and disposed in the connection hole; a second connection chip mounted on a first surface of the second re-distribution layer and disposed in the connection hole; and a first lower semiconductor chip mounted on a second surface, opposite to the first surface, of the second re-distribution layer.