Redistribution Structure Trenches for High-Density Semiconductor Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller and more creative packaging techniques for semiconductor dies to meet demands for miniaturization, higher speed, greater bandwidth, and lower power consumption, particularly in integrating and connecting semiconductor components efficiently.
Innovation Solution
A redistribution structure is developed with multiple dielectric and conductive layers, including a temporary carrier with a release layer, conductive patterns and vias, and a fan-out design, allowing for efficient electrical connections and integration through a series of cutting and bonding processes, including the use of trenches and pre-cut grooves for gas release during heating, ensuring secure bonding and encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If repeated reductions in minimum feature size are used to improve integration density, then more components can be integrated into a given area, but packaging techniques become more challenging and complex
Solution Approach 1:
The patent transitions from traditional planar packaging to three-dimensional vertical stacking architecture. Multiple semiconductor dies are stacked vertically with interconnect structures extending through multiple layers, enabling high-density integration by utilizing the vertical dimension rather than only horizontal plane expansion.
Solution Approach 2:
The patent implements nested packaging where multiple semiconductor dies are stacked within a single package substrate. Each die is positioned at different vertical levels, with lower dies supporting upper dies, creating a nested configuration that maximizes component density within a compact volume.
2Volume of moving object
If smaller packaging techniques are implemented to achieve miniaturization, then device size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment marks and positioning structures that are prepared in advance during die fabrication. These pre-formed features enable precise alignment during the stacking process, reducing the actual manufacturing precision requirements during assembly by having alignment references ready beforehand.
Solution Approach 2:
The patent introduces an intermediate package substrate that acts as a mediator between multiple semiconductor dies. This substrate provides a stable platform with integrated interconnect structures that facilitate precise positioning and alignment of dies during stacking, reducing direct alignment requirements between adjacent dies.
3Quantity of substance
If multiple dielectric and conductive layers are added to improve electrical connectivity, then bandwidth increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs the package substrate to perform multiple functions simultaneously: it provides mechanical support for stacked dies, establishes electrical interconnections between layers through integrated conductive vias, and offers thermal management pathways. This multi-functionality reduces the need for separate dedicated structures for each function.
Solution Approach 2:
The patent combines dielectric layers and conductive interconnect structures into an integrated package substrate architecture. Rather than treating insulation and conduction as separate elements requiring independent fabrication, the substrate integrates both functions in a unified structure that simplifies the overall manufacturing process.
4Quantity of substance
If fan-out design with trenches and pre-cut grooves is used to improve packaging efficiency, then integration density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the package substrate into distinct regions including fan-out areas with pre-cut grooves and trenches. These segmented features create defined zones for different functions: signal routing, mechanical support, and thermal management, allowing each zone to be optimized independently while simplifying the overall manufacturing approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient integration and connection of semiconductor components, reducing delamination and dismount issues, while facilitating high-density packaging and improved electrical connectivity.
Implementation Method 1
a release layer RL formed on a temporary carrier TC
Implementation Method 2
A conductive material layer CM formed on the first conductive pattern RDL1 is heated to form conductive joints 129
Implementation Method 3
Trenches TR1, TR2 provide gas channels from the edge E of the redistribution layer 110 to the center region of the second side S2 of the redistribution layer 110 overlapping with the tape frame TP
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, conductive joints, conductive terminals, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first side and a second side opposite to the first side, wherein trenches are located on the second side of the redistribution structure and extend to an edge of the second side of the redistribution structure. The conductive joints are disposed over the first side of the redistribution structure. The conductive terminals are disposed over the second side of the redistribution structure. The circuit substrate electrically coupled to the redistribution structure through the conductive joints. The insulating encapsulation is disposed on the first side of the redistribution structure to cover the circuit substrate.