Redistribution Via Structure for Reliable Fan-Out Packaging
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Solution Overview
Problem
The reliability of the redistribution circuit structure in integrated fan-out packages is a concern due to the need for compactness and efficient integration of semiconductor components.
Innovation Solution
The fabrication of semiconductor packages involves forming conductive pillars on semiconductor dies, encapsulating them with a protection layer, and then creating a redistribution structure with conductive vias and redistribution wirings, which includes a dielectric layer and a conductive via with a protruding portion having a tapered sidewall to enhance structural strength and contact areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but the structural strength and reliability of the redistribution circuit structure deteriorate
Solution Approach 1:
The conductive via is segmented into two distinct portions: a first portion embedded in the dielectric layer and a second portion protruding from the dielectric layer. This segmentation allows each portion to be optimized independently for its specific function, with the protruding portion providing enhanced mechanical strength and the embedded portion providing electrical connection, thereby resolving the contradiction between miniaturization and structural reliability.
Solution Approach 2:
The conductive via extends in the vertical dimension by protruding from the dielectric layer surface. This dimensional extension increases the contact area and step coverage without increasing the lateral footprint, allowing the structure to maintain high integration density while improving mechanical strength and reliability through increased vertical engagement.
2Reliability
If the contact area of the conductive via is increased to improve reliability, then the structural strength improves, but the area occupied by each component increases, reducing integration density
Solution Approach 1:
The contact area is increased by extending the conductive via vertically in the third dimension rather than expanding it laterally. The protruding portion provides additional contact area and step coverage on the dielectric layer surface without increasing the lateral dimensions, thus maintaining high integration density while improving reliability through increased vertical contact area.
Solution Approach 2:
The protruding portion of the conductive via features a tapered sidewall that transitions from a narrower top to a wider base. This curved, tapered geometry increases the surface area and step coverage compared to a cylindrical via of the same height, providing enhanced mechanical interlocking and electrical connection without requiring additional lateral space.
3Reliability
If the seed layer coverage is increased to improve step coverage and structural strength, then the reliability improves, but the manufacturing complexity and material usage increase
Solution Approach 1:
The dielectric layer is formed to protrude from the semiconductor die surface before the conductive via is formed. This preliminary action creates a pre-formed template that guides the subsequent formation of the conductive via and seed layer, ensuring automatic alignment and optimal step coverage without requiring additional complex manufacturing steps or materials.
Solution Approach 2:
The protruding dielectric layer structure automatically provides the necessary step coverage and mechanical support for the conductive via formation process. The geometry of the protruding portion self-determines the optimal seed layer coverage area, eliminating the need for additional complex patterning or deposition steps to achieve adequate step coverage.
Data Source
AI summary
A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.


