Redistribution Circuit Structure Via Alignment
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and packaging of semiconductor dies due to the need for smaller and more complex redistribution circuit structures that can effectively cope with the increasing integration density and demands for higher speed, bandwidth, and lower power consumption, while maintaining compactness and efficiency.
Innovation Solution
A method for manufacturing semiconductor packages involves forming a redistribution circuit structure with small-sized conductive vias and dielectric layers, using high-resolution photosensitive mask patterns and seed layers to achieve precise electrical connections and alignment, and embedding vias within dielectric layers to ensure efficient electrical connectivity and miniaturization compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging methods are used, then manufacturing simplicity is maintained, but miniaturization and integration density cannot be achieved
Solution Approach 1:
The redistribution circuit structure is segmented into multiple layers with conductive vias connecting each layer. This allows the circuit to be distributed across different planes, enabling miniaturization while maintaining functionality through layered architecture rather than planar expansion
Solution Approach 2:
The patent transitions from two-dimensional planar circuit layouts to three-dimensional layered structures by adding vertical conductive vias that connect conductive patterns across multiple dielectric layers, effectively utilizing the third dimension to achieve higher integration density in a compact footprint
2Manufacturing precision
If via size is reduced for miniaturization, then integration density increases, but alignment precision and manufacturing tolerance deteriorate
Solution Approach 1:
Conductive seeds are formed on the semiconductor die surface before encapsulation, establishing precise alignment references in advance. Subsequent conductive vias are aligned to these pre-formed seeds through the encapsulant, ensuring manufacturing precision even as via sizes are reduced for miniaturization
Solution Approach 2:
The encapsulant acts as an intermediary medium that allows conductive vias to be formed through it and aligned to conductive seeds on the die surface. This intermediary layer enables precise via placement and alignment while accommodating the reduced via sizes needed for miniaturization schemes
3Quantity of substance
If integration density is increased, then component capacity improves, but packaging complexity and difficulty increase
Solution Approach 1:
Multiple semiconductor dies are merged and encapsulated together as a single unit, with redistribution circuits formed across the encapsulated structure to interconnect the dies. This combining approach increases effective integration density while simplifying packaging by treating multiple dies as one integrated package rather than separate components
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor package. Semiconductor dies having conductive pillars are provided and are encapsulated with an insulating encapsulant. A redistribution circuit structure is formed on the insulating encapsulant and the semiconductor dies, and the redistribution circuit structure is electrically connected to the semiconductor dies. A photosensitive mask pattern having a plurality of openings is formed. A plurality of conductive vias is formed within the openings of the photosensitive mask pattern. A dielectric layer is then formed, and the conductive vias are embedded in the dielectric layer.