Multi-Chip Redistribution Structure for Thermal Mismatch Bonding
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving efficient and reliable bonding of chip packages due to warpage and thermal expansion mismatch issues, leading to reduced bonding yield and mechanical strength.
Innovation Solution
The use of an interposer substrate with conductive pads and wiring layers, bonded to a redistribution structure and a chip, where the chip is partially positioned within the interposer substrate, enhances stiffness and reduces warpage, improving bonding yield and mechanical strength by mitigating thermal expansion mismatch stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packaging is used, then manufacturing simplicity is maintained, but warpage and thermal expansion mismatch occur leading to reduced bonding yield and mechanical strength
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between the chip and the substrate. The interposer substrate has a thermal expansion coefficient that matches the chip, and includes through-substrate vias that electrically connect the chip to the substrate. This intermediary structure resolves the thermal expansion mismatch and warpage issues while maintaining reliable electrical connections.
Solution Approach 2:
The package structure employs composite material design where the interposer substrate is made of a material with specific thermal expansion properties that bridge the gap between the chip and substrate materials. This composite approach allows each layer to be optimized for its specific function while collectively solving the thermal and mechanical compatibility issues.
2Productivity
If chip size is increased to improve performance, then functional capability is enhanced, but warpage and thermal stress are exacerbated
Solution Approach 1:
The interposer substrate serves as a mediator that distributes thermal and mechanical stresses across its structure. By positioning the interposer between the large chip and the substrate, it prevents stress concentration and warpage that would otherwise occur with larger chip sizes, thereby maintaining mechanical strength while enabling improved performance.
3Volume of moving object
If package thickness is reduced to improve integration, then space efficiency is improved, but mechanical strength and thermal management become challenging
Solution Approach 1:
The interposer substrate introduces an additional dimensional layer in the vertical stack, allowing thin-film through-substrate via structures to provide robust electrical and mechanical connections. This dimensional approach enables compact packaging while maintaining strength through optimized via designs that extend through the interposer thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases the total thickness of the chip package, improves bonding yield between chip packages, and enhances the mechanical strength and stiffness, thereby addressing the warpage and thermal expansion mismatch issues in existing semiconductor packaging technologies.
Implementation Method 1
thermal expansion mismatch issues, leading to reduced bonding yield and mechanical strength
Implementation Method 2
a conductive via structure passing through the first insulating layer... electrically connected with the conductive pad
Data Source
AI summary
A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure having a conductive pad. The substrate structure includes a first insulating layer under the redistribution structure. The substrate structure includes a conductive via structure passing through the first insulating layer. The conductive via structure is under and electrically connected with the conductive pad. The substrate structure includes a second insulating layer disposed between the redistribution structure and the first insulating layer. The chip package includes a first chip over the redistribution structure and electrically connected to the conductive via structure through the redistribution structure. The chip package includes a second chip under the substrate structure.