Redistribution Via Structure for Thin Semiconductor Packages
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller, faster, and more efficient packaging techniques due to limitations in miniaturization, higher speed, and lower power consumption, particularly in the integration of semiconductor dies and passive devices within existing packaging methods.
Innovation Solution
The proposed solution involves a semiconductor package manufacturing process that includes forming a redistribution structure with alternating conductive and dielectric layers, followed by the placement and bonding of semiconductor dies and passive devices, and subsequent encapsulation, which allows for a reduction in package thickness and improved bonding strength, enabling efficient flip-chip bonding and reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but integration density and miniaturization are limited
Solution Approach 1:
The patent transitions from conventional 2D planar packaging to 3D stacked packaging architecture. Multiple semiconductor dies and passive devices are vertically stacked and interconnected through through-silicon vias (TSVs) and redistribution layers, enabling higher integration density by utilizing the third dimension (vertical stacking) rather than only horizontal expansion.
Solution Approach 2:
The patent implements nested packaging where passive devices (capacitors, inductors) are embedded within or between semiconductor die layers. The encapsulant material is nested around and between all components, providing structural support and protection. This nested arrangement maximizes space utilization and achieves higher integration density within a compact volume.
2Quantity of substance
If feature size is reduced to increase integration density, then more devices fit in a given area, but manufacturing precision and reliability become more challenging
Solution Approach 1:
The patent employs preliminary alignment features such as alignment marks, TSV positioning structures, and pre-defined bonding patterns that are formed during die fabrication. These preliminary structures guide the precise placement and bonding of dies during assembly, ensuring accurate alignment even when feature sizes are reduced. The redistribution layers are also pre-configured with standardized pitch patterns that facilitate precise interconnections.
Solution Approach 2:
The patent utilizes parameter changes in the form of controlled thermal processes during bonding and reflow operations. By precisely controlling temperature profiles, pressure, and time parameters during die bonding and solder reflow, the patent achieves high alignment precision and bonding reliability. The thermal expansion coefficients of different materials are carefully matched and controlled to maintain dimensional stability during manufacturing processes.
3Volume of moving object
If package size is reduced for miniaturization, then smaller devices are achieved, but warpage and bonding strength are compromised
Solution Approach 1:
The patent applies local quality by using different material compositions and structural configurations in different regions of the package. The encapsulant material has varying hardness and thermal expansion properties in different zones to compensate for warpage. TSVs are strategically positioned and sized differently in various regions to balance stress distribution. The redistribution layer thickness and copper fill patterns are locally optimized to reduce warpage while maintaining bonding strength in the compact package structure.
Data Source
AI summary
A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.