Redistribution Structure With Warpage Tuning for Flat Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in maintaining planarity and reducing warpage in advanced packaging technologies like Chip-on-Wafer-on-Substrate (CoWoS) structures due to differences in thermal expansion coefficients of materials, leading to handling difficulties and cold joint issues during manufacturing.
Innovation Solution
A redistribution structure with a warpage tuning layer made of a material with a higher coefficient of thermal expansion than the conductive lines is used to pre-distort the structure at high temperature, counteracting warpage at room temperature and achieving a flat profile, thereby facilitating handling and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging structures are used without warpage tuning layers, then manufacturing is simpler, but warpage occurs at room temperature causing handling difficulties and cold joint issues
Solution Approach 1:
The patent applies preliminary action by forming the warpage tuning layer during the manufacturing process at high temperature to pre-compensate for thermal expansion differences. This preliminary distortion counteracts the warpage that would occur at room temperature, ensuring flatness and preventing handling difficulties and cold joint issues before the product is put into use.
Solution Approach 2:
The patent utilizes thermal expansion by incorporating a warpage tuning layer with specific thermal expansion properties that differ from the carrier and redistribution structure. This layer compensates for thermal mismatch by expanding or contracting at different rates during temperature changes, thereby maintaining planarity and reducing warpage across temperature conditions.
2Ease of operation
If warpage tuning layers are added to compensate for thermal expansion differences, then warpage is reduced and handling is improved, but manufacturing process becomes more complex
Solution Approach 1:
The patent merges the warpage tuning function with the existing redistribution structure by integrating the warpage tuning layer into the same manufacturing process. This combination allows the layer to serve dual purposes: electrical redistribution and warpage compensation, thereby improving handling ease without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent applies parameter changes by adjusting the thickness, material composition, and thermal expansion coefficients of the warpage tuning layer to optimize its compensatory effect. By carefully controlling these parameters, the layer achieves effective warpage reduction while minimizing the impact on manufacturing processes.
3Adaptability or versatility
If materials with different thermal expansion coefficients are used in the packaging structure, then functional integration is enhanced, but warpage and distortion increase
Solution Approach 1:
The patent utilizes thermal expansion by incorporating a warpage tuning layer with specific thermal expansion properties that differ from the carrier and redistribution structure. This layer compensates for thermal mismatch by expanding or contracting at different rates during temperature changes, thereby maintaining planarity and reducing warpage across temperature conditions.
Solution Approach 2:
The patent employs composite materials by creating a multi-layer structure comprising the carrier, warpage tuning layer, and redistribution structure. Each layer is composed of materials with specific properties that, when combined, achieve both functional versatility and dimensional stability, overcoming the warpage issues that arise from using dissimilar materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The warpage tuning layer ensures a planar profile at room temperature, enhancing handling and reducing cold joint defects, thus improving the manufacturing process and product reliability.
Implementation Method 1
differences in thermal expansion coefficients of materials
Implementation Method 2
The bi-metallic layer comprising the conductive line and the warpage tuning layer allows the warpage profile of the structure
Data Source
AI summary
A semiconductor device includes: a die having die connectors at a front side of the die; a molding material around the die; and a redistribution structure, where the die connectors of the die are attached to a first side of the redistribution structure, where the redistribution structure includes: a dielectric layer; a conductive line extending along a first surface of the dielectric layer facing the die; and a warpage tuning layer contacting and extending along a first surface of the conductive line facing the die, where a first coefficient of thermal expansion (CTE) of the conductive line is smaller than a second CTE of the warpage tuning layer.