Redistribution Wiring Stack for Reliable Semiconductor Package Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As electronic devices become smaller and more multifunctional, the reliability of wiring lines in semiconductor packages with diverse line widths is compromised, necessitating a technique to secure and enhance the integrity of these lines.
Innovation Solution
A semiconductor package with a redistribution structure featuring a thick conductive line pattern is developed, incorporating multiple insulating layers and conductive via patterns, where the second conductive line pattern overlaps the first in a vertical direction, improving signal and power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the line widths of wiring lines are diversified and minimum line width is decreased to increase I/O connection terminals, then the integration capacity is improved, but the reliability of wiring lines is compromised
Solution Approach 1:
The patent transitions from a single-layer planar wiring structure to a multi-layer stacked structure where conductive line patterns are arranged in multiple insulating layers. This vertical dimensionality allows increased I/O terminals without reducing minimum line width, as lines in different layers can be densely packed while maintaining structural integrity through vertical stacking rather than horizontal compression.
Solution Approach 2:
The patent employs composite structures combining multiple insulating layers with conductive line patterns embedded within them. This composite approach creates a robust wiring system where the combination of insulating materials and conductive patterns provides both electrical functionality and mechanical strength, enhancing reliability while supporting diversified line widths across multiple layers.
2Adaptability or versatility
If conventional thin wiring lines are used to increase I/O connection terminals, then device integration is improved, but signal and power integrity deteriorates
Solution Approach 1:
The patent resolves the signal and power integrity issue by stacking conductive line patterns vertically across multiple insulating layers. This vertical arrangement allows the effective conductive path thickness to increase without compromising planar integration, as multiple thin layers combine to provide the electrical robustness previously requiring thicker single-layer lines.
Solution Approach 2:
The patent merges multiple thin conductive line patterns from different insulating layers to function collectively as a unified conductive system. This combining effect accumulates the electrical capacity and structural strength of individual thin lines, achieving signal and power integrity equivalent to or exceeding conventional thick single-layer lines while maintaining high device integration.
Data Source
AI summary
A semiconductor package may include a package structure on a redistribution structure. The redistribution structure may include a wiring structure and an insulating structure covering the wiring structure. The package structure may include a semiconductor chip connected to the wiring structure. The insulating structure of the redistribution structure may include a plurality of first insulating layers and a second insulating layer between the plurality of first insulating layers. The plurality of first insulating layers may include at least one of a first conductive line pattern and a first conductive via pattern. The second insulating layer may include a second conductive line pattern overlapping the first conductive line pattern in a vertical direction.